TC9205M
Preliminary Data Sheet
2
Ethernet Media Access Controller
The TC9205M’s Ethernet Media Access Controller (MAC) contains IEEE 802.3 MAC functions for 5 ports.
It is able to operate in 10/100/1000 full duplex and 10/100 half duplex modes for all ports. Each port has
its dedicated receive and transmit FIFO with necessary logic to implement flow control for both duplex
modes. The MAC functions are specially designed for high speed and flexible interfacing.
2.1
Receive MAC
When a frame is received from the Ethernet media through the MII interface, it is stored first in a
dedicated receive FIFO. This FIFO acts as a temporary buffer between the Receive MAC section and
switch core interface.
The Receive MAC layer extracts the valid ethernet information by stripping off the preamble sequence
and SFD of the received frame, which the frame was acquired from the PHY layer via either GMII or MII
interface. The Receive MAC then sends packets with valid information to the receive FIFO.
TC9205M determines the validity of each received packet by checking the CRC and packet length. The
bad packets will be dropped either by the MAC or by the queue manager. Oversized packets are
truncated to 1536 bytes and marked as erroneous packets. Undersized packets are removed from the
receive FIFO without being reported to the switch interface. Therefore the FIFO space held by
undersized packets will be removed automatically.
In Full Duplex mode the Receive MAC can identify any received frame as a flow control frame having a
valid CRC. It will load its internal pause counter with the ‘pause quanta’ value extracted from the
incoming frame. The flow control frame will be rejected after the pausing period has been acquired. After
the pausing period has obtained from the flow control frame, the flow control mechanism inside
TC9205M will set a decremental timer in the pause counter according to the value of the pausing period.
A non-zero value sets in the pause counter will issue the Receive MAC to XOFF (Transmit Stop) the
Transmit MAC. The pause counter will decrement the ‘pause quanta’ value after each slot time until it
reaches zero. If the pause quanta value is equal to zero the flow control mechanism will XON (Transmit
Enable) the Transmit MAC.
If a frame transmission is in progress when the PAUSE frame is received, the transmission is allowed to
complete for the current transmitting frame but the transmission for the next frame(s) will hold until the
Receive MAC generates an XON command. The pause time will begin at the end of current transmission
or start immediately if no transmission is in the medium when the PAUSE frame is received. If a pause
command is received while the transmitter is already in pause, the new pause time indicated by the new
Flow Control frame will be loaded into the pause register.
The MAC is also able to reject frames containing IEEE 802.1D Reserved Group Destination Addresses
and frames with Mac Control Type (Type 88-08) if selected through configuration settings.
When the receive FIFO is full and additional data are still incoming from the MAC, then the overrun
condition occurs and the frame is dropped. If the system clock frequency is not lower than the
recommended value this condition will never occur.
Confidential.
15/51
July 30, 2003
Copyright © 2003, IC Plus Corp.
TC9205M-DS-R03
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