TC9205M
Preliminary Data Sheet
2.2
Transmit MAC
The Transmit MAC section assembles the MAC frames stored in the transmit FIFO and controls their
transmission onto the media via external PHY entities. It appends the standard preamble and start of
frame delimiter to the transmitted packets. The MAC also controls the interframe gap time during
transmission, maintaining for default the standard minimum interframe gap of 96-bit time. This value can
be changed in the EEPROM register setting.
For Half Duplex mode the Transmit MAC meets CSMA/CD IEEE 802.3 requirements. The FIFO logic
manages frame retransmission for early collision conditions or discards the frame if late collision occurs.
It also follows the truncated binary exponential backoff algorithm, collision and jamming procedures.
The transmit FIFO stores the packets which are ready for transmission in the main memory queues. If
there is no packet ready in the transmit FIFO before the current packet completes its transmission, an
underrun condition has occurred and the mechanism will generate a signal to indicate FIFO underrun
event, but if the switch core transfers the rest of the packet(s) into the FIFO, the Transmit MAC will safely
discard it without affecting the next packet. Underrun conditions never occur if the system is operating at
the recommended clock frequency or higher.
For full duplex mode TC9205M implements the flow control algorithm according to the IEEE 802.3x standard,
using the XON/XOFF method. Full duplex flow control can be configured automatically, by auto-negotiation
result, or manually, pin configuration and/or EEPROM settings, to enable/disable the function.
The TC9205M executes backpressure algorithm for half duplex flow control supporting both collision
based and carrier based backpressure. Both modes are based on carrier sense forced collisions and an
aggressive backoff algorithm. The forced consecutive collisions generated for flow control purposes can
be limited to a maximum of 28 collisions if this option is selected. This feature helps to avoid HUB
partitioning in heavy traffic. The number of collisions can be adjusted in EEPROM settings.
MAC Block Diagram
Rx FIFO
Rx MAC
Tx MAC
Flow
Control
Tx FIFO
Fifo Control Logic
System Interface
MAC
RMII
PHY Layer
RMII Rx Data (2)
Tx Data (64)
FC Insert
Tim e Value (16)
Rx Data (64)
RMII Tx Data (2)
Confidential.
16/51
July 30, 2003
Copyright © 2003, IC Plus Corp.
TC9205M-DS-R03
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