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SSM3J56ACT 数据表(PDF) 3 Page - Toshiba Semiconductor |
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SSM3J56ACT 数据表(HTML) 3 Page - Toshiba Semiconductor |
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3 / 9 page ![]() SSM3J56ACT 3 5. 5. 5. 5. Electrical Characteristics Electrical Characteristics Electrical Characteristics Electrical Characteristics 5.1. 5.1. 5.1. 5.1. Static Characteristics (Unless otherwise specified, T Static Characteristics (Unless otherwise specified, T Static Characteristics (Unless otherwise specified, T Static Characteristics (Unless otherwise specified, Taaaa = 25 = 25 = 25 = 25 )))) Characteristics Gate leakage current Drain cut-off current Drain-source breakdown voltage Drain-source breakdown voltage Gate threshold voltage Drain-source on-resistance Forward transfer admittance (Note 1) (Note 2) (Note 3) (Note 3) Symbol IGSS IDSS V(BR)DSS V(BR)DSX Vth RDS(ON) |Yfs| Test Condition VGS = ±8 V, VDS = 0 V VDS = -20 V, VGS = 0 V ID = -1 mA, VGS = 0 V ID = -1 mA, VGS = 5 V VDS = -3 V, ID = -1 mA ID = -800 mA, VGS = -4.5 V ID = -500 mA, VGS = -2.5 V ID = -200 mA, VGS = -1.8 V ID = -100 mA, VGS = -1.5 V ID = -10 mA, VGS = -1.2 V VDS = -3 V, ID = -100 mA Min -20 -15 -0.3 0.5 Typ. 310 380 470 560 770 1.0 Max ±1 -1 -1.0 390 480 660 900 4000 Unit µA µA V V V mΩ S Note 1: If a forward bias is applied between gate and source, this device enters V(BR)DSX mode. Note that the drain- source breakdown voltage is lowered in this mode. Note 2: Let Vth be the voltage applied between gate and source that causes the drain current (ID) to below (-1 mA for this device). Then, for normal switching operation, VGS(ON) must be higher than Vth, and VGS(OFF) must be lower than Vth. This relationship can be expressed as: VGS(OFF) < Vth < VGS(ON). Take this into consideration when using the device. Note 3: Pulse measurement. 5.2. 5.2. 5.2. 5.2. Dynamic Characteristics (Unless otherwise specified, T Dynamic Characteristics (Unless otherwise specified, T Dynamic Characteristics (Unless otherwise specified, T Dynamic Characteristics (Unless otherwise specified, Taaaa = 25 = 25 = 25 = 25 )))) Characteristics Input capacitance Reverse transfer capacitance Output capacitance Switching time (turn-on time) Switching time (turn-off time) Symbol Ciss Crss Coss ton toff Test Condition VDS = -10 V, VGS = 0 V, f = 1 MHz VDD = -10 V, ID = -200 mA VGS = 0 to -2.5 V, RG = 50 Ω Duty ≤ 1 %, VIN: tr, tf < 5 ns, Common source, See Chapter 5.3. Min Typ. 100 10 16 8 26 Max Unit pF ns 5.3. 5.3. 5.3. 5.3. Switching Time Test Circuit Switching Time Test Circuit Switching Time Test Circuit Switching Time Test Circuit Fig. Fig. Fig. Fig. 5.3.1 5.3.1 5.3.1 5.3.1 Switching Time Test Circuit Switching Time Test Circuit Switching Time Test Circuit Switching Time Test Circuit Fig. Fig. Fig. Fig. 5.3.2 5.3.2 5.3.2 5.3.2 Input Waveform/Output Waveform Input Waveform/Output Waveform Input Waveform/Output Waveform Input Waveform/Output Waveform 2016-09-13 Rev.2.0 ©2015 Toshiba Corporation |
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