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FEATURES…

The SP8480 Series are complete data acquisi-

tion systems, featuring 8-channel multiplexer,

internal reference and 12-bit sampling A/D con-

verter implemented as a single monolithic IC.

The analog multiplexer accepts 0V to +5V uni-

polar full scale inputs. Output data is formatted

as an 8-bit/4-bit nibble.

Linearity errors of

±0.5 and ±1.0 LSB, and

Differential Non-linearity to 12-bits is guaran-

teed, with no missing codes over temperature.

Channel-to-channel crosstalk is typically -85dB.

Multiplexer settling plus acquisition time is 1.9

µs

maximum; A/D conversion time is 8.1

µs maxi-

mum.

Versions of the SP8480 are available in 28-pin

plastic DIP, ceramic DIP or SOIC packages.

Operating temperature ranges are 0

°C to +70°C

commercial and -40

°C to +85°C industrial.

The SAR, timed by the clock, sequences through

the conversion cycle and returns an end–of–

convert flag to the control section of the ADC.

The clock is then disabled by the control section,

which puts the STATUS output line low. The

control section is enabled to allow the data to be

read by external command (R/C).

Multiplexer Control and Inputs

On the SP8480 the multiplexer is independent

of any other control line. The address line latches

MA

mode in the SP8480, and are therefore transpar-

ent. Data setup time for these inputs is 50ns. If

a device is required with additional MUX con-

trol, please refer to the Sipex SP8481 DAS.

Since the latches are enabled, MUX channel

select data need not be held by the bus for a

minimum period of 3.0

µs after the conversion

has been initiated. This is the time required for

the MUX and Sample and Hold to settle. How-

ever it is advisable that the MUX not be changed

at all during the full 10

µs conversion time due to

capacitive coupling effects of digital edges

through the silicon.

The SP8480 multiplexer inputs have been de-

signed to allow substantial overvoltage condi-

tions to occur without any damage. The inputs

are diode-clamped and further protected with a

200

Ω series resistor. As a result, momentary (10

seconds) input voltages can be as low as -16.5V

or as high as +31.5V with no change or degrada-

tion in multiplexer performance or crosstalk.

This feature allows the output voltage of an

externally connected op amp to swing to

±15V

supply levels with no multiplexer damage. Com-

plicated power-up sequencing is not required to

protect the SP8480. The multiplexer inputs may

be damaged, however, if the inputs are allowed

to either source or sink greater than 100mA.

Initiating A Conversion

Please refer to Figure 4. The SP8480 was de-

signed to require a minimum of control to per-

form a 12-bit conversion. The control input used

is R/C which tri-states the outputs and starts the

conversion when low. The STATUS line indi-

cates when a conversion is in process and when

it is complete. The A

0

control input is used to

CIRCUIT OPERATION…

The SP8480 is a complete 8-channel data acqui-

sition systems (DAS), with on-board

multi-

plexer, voltage reference, sample-and-hold, clock

and tri-state outputs. The digital control archi-

tecture is very similar to the industry-standard

574-type A/D, and uses identical control lines

and digital states.

The multiplexer for the SP8480 is identical in

operation to many discrete devices available

today, except that it has been integrated into the

single-chip DAS. The appropriate channel is

selected using the MUX address lines MA

MA

analog input is fed through to the ADC. The

input impedance into any MUX channel will be

the integral sampling structure of the capacitor

DAC. Crosstalk is kept to -85dB at 0V to 5V

p-p

over an input frequency range of 10kHz to 50kHz.

When the internal control section of the SP8480

initiates a conversion command the internal clock

is enabled, and the successive approximation

register (SAR) is reset to all zeros. Once the

conversion has been started it cannot be stopped

or restarted. Data is not available at the output

buffers until the conversion has been completed.