数据搜索系统，热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

预览 PDF HTML

P9225-R 数据表(PDF) 27 Page - Integrated Device Technology

部件名 P9225-R
功能描述  Dual-Mode Wireless Power Receiver
PDF  34 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  IDT [Integrated Device Technology]
网页  http://www.idt.com
标志 IDT - Integrated Device Technology

P9225-R 数据表(HTML) 27 Page - Integrated Device Technology

Back Button P9225-R Datasheet HTML 23Page - Integrated Device Technology P9225-R Datasheet HTML 24Page - Integrated Device Technology P9225-R Datasheet HTML 25Page - Integrated Device Technology P9225-R Datasheet HTML 26Page - Integrated Device Technology P9225-R Datasheet HTML 27Page - Integrated Device Technology P9225-R Datasheet HTML 28Page - Integrated Device Technology P9225-R Datasheet HTML 29Page - Integrated Device Technology P9225-R Datasheet HTML 30Page - Integrated Device Technology P9225-R Datasheet HTML 31Page - Integrated Device Technology Next Button
Zoom Inzoom in Zoom Outzoom out
 27 / 34 page
background image
P9225-R Datasheet
© 2018 Integrated Device Technology, Inc.
27
November 12, 2018
Table 23. Clear Interrupt Bits
Address and Bit
Register or Bit Field Name
R/W
Default
Function and Description
0056HEX [7]
Clear_Vout_Changed_Bit
RW
0BIN
“1” clears the INT_Vout_Status bit in register 0036HEX (refer to
Table 13). Register 0036HEX is updated after the application
processor resets the interrupt pin by writing “1” to bit 5 of register
004EHEX (refer to Table 22).
0056HEX [6]
Reserved
RW
0BIN
0056HEX [5]
Reserved
RW
0BIN
0056HEX [4]
Reserved
RW
0BIN
0056HEX [3]
Reserved
RW
0BIN
0056HEX [2]
Clear_Over_Temperature_Bit
RW
0BIN
“1” clears the INT_OVER_TEMP_Status bit in register 0036HEX.
Register 0036HEX is updated after the application processor
resets the interrupt pin by writing“1” to bit 5 of register 004EHEX.
0056HEX [1]
Clear_Over_Voltage_Bit
RW
0BIN
“1” clears the INT_VRECT_OV_Status bit in register 0036HEX.
Register 0036HEX is updated after the application processor
resets the interrupt pin by writing “1” to bit 5 of register 004EHEX.
0056HEX [0]
Clear_Over_Current_Bit
RW
0BIN
“1” clears the INT_OC_Limit_Status bit in register 0036HEX.
Register 0036HEX is updated after the application processor
resets the interrupt pin by writing “1” to bit 5 of register 004EHEX.
Table 24. WPC Power Transfer Phase Indicator Register
Address and Bits
Register Field Name
R/W
Default
Function and Description
014AHEX
System_State
R
00HEX
0DEC = Selection Phase
1DEC = Identification Phase
2DEC = Configuration Phase
3DEC = Reserved
4DEC = Reserved
5DEC = Power Transfer Phase
6DEC = Reserved
7DEC = Reserved
8 DEC = Error State



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com