P9225-R Datasheet

© 2018 Integrated Device Technology, Inc.

3

November 12, 2018

16. Marking Diagram ........................................................................................................................................................................................33

17. Ordering Information...................................................................................................................................................................................33

18. Revision History..........................................................................................................................................................................................34

List of Figures

Figure 1. Pin Assignments – Bottom View..........................................................................................................................................................5

Figure 2. Efficiency vs Output Load: VOUT = 5.5V.............................................................................................................................................12

Figure 3. VOUT vs Output Load: VOUT = 5.5V.....................................................................................................................................................12

Figure 4. Efficiency vs Output Load: VOUT = 5V................................................................................................................................................12

Figure 5. VOUT vs Output Load: VOUT = 5V........................................................................................................................................................12

Figure 6. Efficiency vs Output Load: VOUT = 4.5V.............................................................................................................................................12

Figure 7. VOUT vs Output Load: VOUT = 4.5V.....................................................................................................................................................12

Figure 8. Rectified Voltage vs Output Load......................................................................................................................................................13

Figure 9. Load Transient: VOUT = 5.5V, 0A  1.2A...........................................................................................................................................13

Figure 10. Load Transient: VOUT = 5.5V, 1.2A  0A...........................................................................................................................................13

Figure 11. Load Transient: VOUT = 5V, 0A  1.2A..............................................................................................................................................13

Figure 12. Load Transient: VOUT = 5V, 1.2A  0A..............................................................................................................................................13

Figure 13. Load Transient: VOUT = 4.5V, 0A  1.2A...........................................................................................................................................14

Figure 14. Load Transient: VOUT = 4.5V, 1.2A  0A...........................................................................................................................................14

Figure 15. Functional Block Diagram..................................................................................................................................................................15

Figure 16. Bit Encoding Scheme ........................................................................................................................................................................20

Figure 17. Byte Encoding Scheme .....................................................................................................................................................................20

Figure 18. Communication Packet Structure......................................................................................................................................................20

Figure 19. State Diagram for WPC Baseline Power Profile (BPP) Operation.....................................................................................................21

Figure 20. I2C Access Read Protocol.................................................................................................................................................................28

Figure 21. I2C Access Write Protocol.................................................................................................................................................................28

Figure 22. P9225-R Typical Application Schematic............................................................................................................................................31

List of Tables

Table 1. Pin Descriptions...................................................................................................................................................................................6

Table 2. Absolute Maximum Ratings.................................................................................................................................................................8

Table 3. ESD Information ..................................................................................................................................................................................8

Table 4. Package Thermal Information .............................................................................................................................................................9

Table 5. Electrical Characteristics .....................................................................................................................................................................9

Table 6. Setting the Output Voltage ................................................................................................................................................................16

Table 7. Setting the Current Limit....................................................................................................................................................................17

Table 8. Maximum Estimated Power Loss ......................................................................................................................................................19

Table 9. Device Identification Register............................................................................................................................................................23

Table 10. Firmware Major Revision...................................................................................................................................................................23