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P9225-R-EVK 数据表(PDF) 10 Page - Integrated Device Technology

部件名 P9225-R-EVK
功能描述  Dual-Mode Wireless Power Receiver
PDF  34 Pages
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制造商  IDT [Integrated Device Technology]
网页  http://www.idt.com
标志 IDT - Integrated Device Technology

P9225-R-EVK 数据表(HTML) 10 Page - Integrated Device Technology

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P9225-R Datasheet
© 2018 Integrated Device Technology, Inc.
10
November 12, 2018
Symbol
Description
Conditions
Minimum
Typical
Maximum
Units
Low Drop-Out (LDO) Regulator
IOUT_MAX
Maximum Output Current
1.25
A
VOUT_5V
5V Output Voltage
VOSET= 1.8V, VRECT=5.5V
5
V
Analog to Digital Converter
N
Resolution
12
Bit
fSAMPLE
Sampling Rate
67.5
kSa/s
Channel
Number of Channels
8
VIN,FS
Full-Scale Input Voltage
2.1
V
EN
����Pin
VIH_EN¯¯
Input Threshold HIGH
1.4
V
VIL_EN¯¯
Input Threshold LOW
0.25
V
IIL_EN¯¯
Input Current LOW
VEN
¯¯
= 0V
-1
1
μA
IIH_EN
¯¯
Input Current HIGH
VEN
¯¯
= 5V
2.5
μA
EOC pin
VIH_EOC
Input Threshold HIGH
1.4
V
VIL_EOC
Input Threshold LOW
0.7
V
IIL_EOC
Input Current LOW
VEOC= 0V
-1
1
μA
IIH_EOC
Input Current HIGH
VEOC= 1.8V
-1
1
μA
VOSET, ILIM, TS, RPPO, RPPG
IIL
Input Current LOW
VVOSET, VILIM, VTS, VRPPO, VRPPG = 0V
-1
1
µA
IIH
Input Current HIGH
VVOSET, VILIM, VTS, VRPPO, VRPPG = 1.8V
-1
1
µA
INT
����pin
ILKG
Input Leakage Current
VINT
�=0Vand5V
-1
1
µA
VOL
Output Logic LOW
IOL = 8mA
0.36
V
I2C Interface – SCL, SDA
VIL
Input Threshold LOW
0.7
V
VIH
Input Threshold HIGH
1.4
V
ILKG
Input Leakage Current
VSCL, VSDA = 0V and 5V
-1
1
µA
VOL
Output Logic LOW
IOL = 8mA
0.36
V
fSCL
Clock Frequency
400
kHz
tHD,STA
Hold Time (Repeated) for
START Condition
0.6
µs
tHD:DAT
Data Hold Time
0
ns
tLOW
Clock Low Period
1.3
µs
tHIGH
Clock High Period
0.6
µs



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