THEVA12LVDR1020 datasheet(4/8 Pages) CEL

4 / 8 page

Output Clock Delay Timing Select.

Pin#

PinName

SW403 Setting

Pin#

Def.

NodeName

THC63LVD1024

Description

* Def. : Default Setting

THEVA12LVDR1020 Mode Setting & LVDS-Cable

THine Electronics, Inc.

2011/04/14

Output Clock Delay Timing Select.

tDOUT=Output Data Cycle

SW-Pin#

-6

tDOUT

H(open)

RxDK1

Offset[nsec]

MODE[1:0]

H(open)

tDOUT

H(open)

H(open) H(open)

MODE1

MODE0

Mode

Single Link(Single-in/Single-out)

Single Link(Single-in/Dual-out)

Pixel Data Mode.

MODE1

H(open)

-7

tDOUT

RxMD1DK2

Must be tied to VCC.

Single Link(Single in/Dual out)

Dual Link(Dual-in/Single-out)

MODE0

Dual Link(Dual-in/Single-out)

Reserved

RxMD0RF2

RxOE2

/PDWN

Power down and Output Control.

H : Normal operation

L : Power down

6RxPDWN

Ground Pins for LVDS inputs.

LVDS mapping table select.

H : Mapping Mode1

L : Mapping Mode2

* Def. : Default Setting

Pin#

144

RxTEST

MAP

PinName

Description

LLGND

Def.

NodeName

THC63LVD1024

Pin#

RxMAP

SW404 Setting

DDR function enable.

L : Mapping Mode2

Must be tied to GND

DDR (Double Edge Output) function disable.

DDR (Double Edge Output) function enable.

Mode

MODE2

MODE<1:0>

MODE2

RxMD2

Output Enable.

H : Output enable,

L : Output disable

Output Clock Triggering Edge Select.

H : Rising edge.

L : Falling edge.

5N/C

R/F

RxOE1

RxRF1

N/C

Non Connected

N/C

3/5

THEVA12LVDR1020 manual Rev 1 00 E

N/C

3/5

THEVA12LVDR1020_manual_Rev.1.00_E

THEVA12LVDR1020 数据表(PDF) 4 Page - California Eastern Labs

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THEVA12LVDR1020 数据表(PDF) 4 Page - California Eastern Labs

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