Application Information

TS4975

18/33

4

Application Information

The TS4975 integrates 2 monolithic power amplifiers. The amplifier output can be configured

as either SE (single-ended) capacitively-coupled output or PHG (phantom ground) output.

In a SE configuration an output capacitor, Cout, on each output is needed. This output coupling

capacitor blocks the Vcc/2 voltage (to which the output amplifier is biased) and couples the

audio signal to the load.

In a PHG configuration, internal buffers are connected to PHG1 and PHG2 pins biased to the

Vcc/2 voltage, and output amplifiers are also biased to the Vcc/2 voltage. Therefore, no output

capacitors are needed. The advantage of the PHG configuration is fewer external components

compared with a SE configuration. However, note that the device has higher power dissipation

(see Power dissipation and efficiency on page 22).

This chapter gives information on how to configure the TS4975 in application.

4.1

I²C bus interface

Table 8.

I²C bus interface pin descriptions

4.1.1

I²C bus operation

The TS4975 uses a serial bus, which conforms to the I²C protocol, to control the chip’s

functions with two wires: Clock and Data. The Clock line is uni-directional. The Data line is bi-

directional (open-collector) with an external chip pull-up resistor (typically 10 kOhm). The

maximum clock frequency specified by the I²C standard is 400kHz.

Table 9.

Device slave address

The host MCU can write into the TS4975 control registers and read from the control registers.

The slave address of the TS4975 for writing is CC or CE hex. In order to write data into the

TS4975, after the “start” message, the MCU must send the following data:

●

send the I²C address slave byte with a low level for the R/W bit

●

send the data

Pin

Functional Description

SDA

This is the serial data input pin

SCL

This is the clock input pin

ADD

User-setable portion of device’s I2C address

A6

A5

A4

A3

A2

A1

A0

Rw

110

0

1

1

A0

X