TS4975

Application Information

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Table 13.

Stand-by mode I²C condition

Table 14.

I²C control byte states

4.1.3

Acknowledge

The number of data bytes transferred between the start and the stop conditions from the CPU

master to the TS4975 slave is not limited. Each byte of eight bits is followed by one

acknowledge bit.

The TS4975 which is addressed, generates an acknowledge after the reception of each byte

that has been clocked out.

D7

(MSB)

D6

D5

D4

D3

D2

D1

D0

0

0

0

0

X

XXX

D7

(MSB)

D6

D5

D4

D3

D2

D1

D0

1

1

1

1

x

X

X

X

Undefined State