ST7282 datasheet(18/23 Pages) STMICROELECTRONICS

18 / 23 page

ST7282A5 - ST7282B5 - ROM FROM EPROM

Family

Issuer Ref.

Chrono

March 26, 1997

Previous Ref

Edition

ST7

PG-RO

97115

7282A5B5

Target C

Page 18/23

PA4 does not have a pull-up resistor.

Ports PD0 ... PD7, PE0 ... PE3, PF0 ... PF7, PG0

... PG7 and PH0 ... PH7 are in the "LCD Output

mode" (all pins switched to VSS).

PC7 is switched to analog input mode during reset

( data register and option register bits are set ).

PC0, PC1 may optionally be used to "cascade" the

LCD (refer to: 2. LCD CONTROLLER/DRIVER).

2.6 ADC

The reference voltage inputs of the ADC1N are

connected to VDDA, VSSA. Therefore special care

has to be taken to stabilize VDDA, VSSA and to

avoid switching of I/O pins during conversion. An-

alog inputs may be multiplexed from pins PA0 ...

PA7, PB0 ... PB7 and PC0 ... PC7. Up to 24 ana-

log inputs can be multiplexed.

Selection of an analog input is done by program-

ming the corresponding pin of a port as analog in-

put ( DDR = 0, DR = 1, OPR = 1 ). Be sure that

only one port pin is programmed as analog input at

a time. Otherwise the analog sources are shorted

by the analog multiplexer. Conversion time for an

8.55 MHz clock is 34

µsec (i.e. 288 clocks + 0...6

clocks of fOSC) because the ADC is supplied with

a clock signal of fOSC : 6 that is also available dur-

ing WAIT. The ADC interrupt is connected to level

sensitive interrupt input I5 of the core ( start ad-

dress FFF2H ). So the interrupt has to be cleared

before the interrupt service routine is left.

A stop instruction will stop the clock of the ADC

and will switch off its comparator to achieve mini-

mum power consumption. This can also be done

by clearing bit 5 ( SC ) of ADC control register (

10H ).

A rising edge on EOC-bit sets the interrupt flipflop.

To remove the interrupt, a write operation to ADC-

Control register has to be executed, to clear the in-

terrupt flipflop. After the reset, the interrupt flipflop

is also cleared.

2.7 SERIAL I/O

The 8 bit SIO generates an interrupt after the fall-

ing edge of the eight external clock pulse. The in-

terrupt signals to the ST72 to read or write the SIO

via an 8 bit register ( adr. 26H ).

The SIO uses the input/output structure of Port A (

PA5 : SCL, PA6 : SDA, PA7 : DOUT ) (see fig. 2).

The 3 pins can be operated in the following ways:

directly by software, as an S-BUS, as an I

2C-BUS

and as a standard SIO ( clock, data, enable ).

To operate the SIO PA5 and PA6 have to be pro-

grammed as inputs, PA7 as open drain output.

The SIO interrupt ( active low ) is connected to the

interrupt input I3 of the core ( address FFF6H ).

After reset all ports are in input mode with pull up

resistors switched on and the SIO interrupt is disa-

bled.

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