ST7282A5 - ST7282B5 - ROM FROM EPROM

Family

Issuer Ref.

Chrono

March 26, 1997

Previous Ref

Edition

ST7

PG-RO

97115

7282A5B5

Target C

Page 20/23

Before access to one area, also the control regis-

ter of the other area should be checked and ac-

cess done only, if both areas allow the required ac-

cess.

SGS-THOMSON may implement a single or dou-

ble register version in future ROM or EPROM ver-

sions.

2.10 32K ROM

The 32K ROM is located at addresses 8000H-FFFFH.

16 bytes ( FFE0H - FFEFH ) are reserved for SGS-Thomson test vectors.

2.11 RDS

Modules ( see separate specs )

Registers of all RDS-Modules should not be accessed ( read or write ) during slow mode of CPU.

2.12 OSCILLATOR

The ST7 Oscillator allows operation with a crystal

or external input. The corresponding mode is de-

fined by a metal option. In case of external input

the clock amplitude into OSCI may not be lower

then 50mV. The pin OSCO/STOP then is serving

as output for the stop signal to synchronize with

external clock sources.

In the present version, the device works with a

dedicated crystal.

0E00

0FFF

Reg

future

Adr. 14H

Adr. 15H

EEAREA

EEAREA

0E00

0EFF

0F00

0FFF

Reg

Reg

Adr. 14H

Adr. 15H

PADD.DS4