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USBLC6-4SC6 数据表(PDF) 5 Page - STMicroelectronics

部件名 USBLC6-4SC6
功能描述  VERY LOW CAPACITANCE ESD PROTECTION
PDF  10 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

USBLC6-4SC6 数据表(HTML) 5 Page - STMicroelectronics

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3. HOW TO ENSURE A GOOD ESD PROTECTION
While the USBLC6-4SC6 provides a high immunity to ESD surge, an efficient protection depends on the
layout of the board. In the same way, with the rail to rail topology, the track from the VBUS pin to the power
supply +VCC and from the VBUS pin to GND must be as short as possible to avoid overvoltages due to
parasitic phenomena (see figure 6).
It’s often harder to connect the power supply near to the USBLC6-4SC6 unlike the ground thanks to the
ground plane that allows a short connection.
To ensure the same efficiency for positive surges when the connections can’t be short enough, we
recommend to put close to the USBLC6-4SC6, between VBUS and ground, a capacitance of 100nF to
prevent from these kinds of overvoltage disturbances (see figure 7).
The add of this capacitance will allow a better protection by providing during surge a constant voltage.
The figures 8, 9 and 10 show the improvement of the ESD protection according to the recommendations
described above.
IMPORTANT:
A main precaution to take is to put the protection device closer to the disturbance source (generally the
connector).
Note: The measurements have been done with the USBLC6-4SC6 in open circuit.
Figure 7: ESD behavior: optimized layout and
add of a capacitance of 100nF
Figure
8:
ESD
behavior:
measurements
conditions (with coupling capacitance)
Figure
9:
Remaining
voltage
after
the
USBLC6-4SC6 during positive ESD surge
Figure
10:
Remaining
voltage
after
the
USBLC6-4SC6 during negative ESD surge
REF1=GND
VI/O
ESD
SURGE
I/O
REF2=+
VCC
C=100nF
Lw
V+
V
CL
CC
F
V+
=
surge >0
surge <0
VV
CL
F
-
- =
t
V+
CL
POSITIVE
SURGE
t
V-
CL
NEGATIVE
SURGE
+5V
C=100nF
TEST BOARD
ESD
SURGE



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