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High Speed Super Low Power SRAM
32K-Word By 8 Bit
CS18LV02565
3
Rev. 2.0
Chiplus reserves the right to change product or specification without notice.
PIN CONFIGURATIONS
OE
A10
A11
A9
A8
A13
WE
VCC
A14
A12
A7
A6
A5
A4
A3
CE
DQ7
DQ6
DQ5
DQ4
DQ3
GND
DQ2
DQ1
DQ0
A0
A1
A2
27
20
15
16
17
18
19
21
22
23
24
25
26
28
2
9
12
14
13
11
10
6
8
7
5
4
3
1
28TSOP(I)-8x13.4mm
FUNCTIONAL BLOCK DIAGRAM
Address
Input
Buffer
Row
Decoder
512x512
Memory Array
Data Output
Buffer
Write Driver
Sense Amp
Column Decoder
Address Input Buffer
Control
Column I/O
Data Input
Buffer
A6
A7
A8
A9
A11
A12
A13
DQ0
DQ7
18
512
8
8
88
512
64
12
A0 A1 A2 A3 A4 A10
/WE
/OE
/CE
VCC
GND
A5
A14