TPS1663 datasheet(7/43 Pages) TI1

7 / 43 page

TPS1663

www.ti.com

SLVSET9D – SEPTEMBER 2018 – REVISED AUGUST 2019

Product Folder Links: TPS1663

Submit Documentation Feedback

Electrical Characteristics (continued)

–40°C

≤ TA = TJ ≤ +125°C, 4.5 V < V(IN) = V(P_IN) < 60 V, V(SHDN) = 2 V, R(ILIM) = 30 kΩ, IMON = PGOOD = FLT = OPEN, C(OUT)

= 1 μF, C(dVdT) = OPEN. (All voltages referenced to GND, (unless otherwise noted))

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

LOW IQ SHUTDOWN (SHDN) INPUT

V(SHDN)

Open circuit voltage

I(SHDN) = 0.1 µA

2.48

2.7

3.3

V(SHUTF)

SHDN threshold voltage for low IQ

shutdown, falling

0.8

V(SHUTR)

SHDN threshold rising

I(SHDN)

Leakage current

V(SHDN) = 0 V

–10

µA

FAULT FLAG (FLT): ACTIVE LOW

R(FLT)

FLT Pull-down resistance

130

I(FLT)

FLT Input leakage current

0 V

≤ V(FLT) ≤ 60 V

–150

150

POWER GOOD (PGOOD)

R(PGOOD)

PGOOD Pull-down resistance

130

I(PGOOD)

PGOOD Input leakage current

0 V

≤ V(PGOOD) ≤ 60 V

–150

150

THERMAL PROTECTION

T(J_REG)

Thermal regulation set point

136

145

154

ºC

T(TSD)

Thermal shutdown (TSD) threshold,

rising

165

ºC

T(TSDhyst)

TSD hysteresis

ºC

MODE

MODE_SEL

Mode selection

MODE = Open

Latch

MODE = Short to GND

Auto –

Retry

7.6 Timing Requirements

–40°C

≤ TA = TJ ≤ +125°C, 4.5 V < V(IN) = V(P_IN) < 60 V, V(SHDN) = 2 V, R(ILIM) = 30 kΩ, IMON = PGOOD = FLT = OPEN, C(OUT)

= 1 μF, C(dVdT) = OPEN. (All voltages referenced to GND, (unless otherwise noted))

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX

UNIT

UVLO INPUT (UVLO)

UVLO_ton(dly)

UVLO switch turnon delay

UVLO

↑ (100 mV above V(UVLOR)) to

V(OUT) = 100 mV , C(dVdT) ≥ 10 nF,

[C(dVdT) in nF]

742 +

49.5 x

C(dVdT)

µs

UVLO_toff(dly)

UVLO switch turnoff delay

UVLO

↓(20 mV below V(UVLOF)) to FLT↓

µs

tUVLO_FLT(dly)

UVLO to Fault de-assertion delay

UVLO

↑ to FLT ↑ delay

500

617

700

µs

OVER VOLTAGE PROTECTION INPUT (OVP)

OVP_toff(dly)

OVP switch turnOFF delay

OVP

↑ (20 mV above V(OVPR)) to FLT↓

8.5

µs

OVP_ton(dly)

OVP switch disable delay

OVP

↓ (100 mV below V(OVPF)) to FET

ON , C(dVdT) ≥ 10 nF, [C(dVdT) in nF]

150 +

49.5 x

C(dVdT)

µs

tOVC(dly)

Maximum duration in over voltage

clamp operation

TPS16632 Only

162

OVC_tFLT(dly)

FLT assertion delay in over voltage

clamp operation

TPS16632 Only

617

µs

SHUTDOWN CONTROL INPUT (SHDN)

tSD(dly)

SHUTDOWN entry delay

SHDN

↓ (below V(SHUTF)) to FET OFF

0.8

1.5

µs

CURRENT LIMIT

tFASTTRIP(dly)

Hot-short response time

I(OUT) > I(SCP)

µs

Soft short response

I(FASTTRIP) < I(OUT) < I(SCP)

2.2

3.2

4.5

µs

tCL_PLIM(dly)

Maximum duration in current & (power

limiting: TPS16632 Only)

129

162

202

TPS1663 数据表(PDF) 7 Page - Texas Instruments

TPS1663 数据表(HTML) 7 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

数据表下载

链接网址

TPS1663 数据表(PDF) 7 Page - Texas Instruments

TPS1663 数据表(HTML) 7 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

数据表 下载

链接网址

数据表下载