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56F8167 数据表(PDF) 166 Page - Freescale Semiconductor, Inc |
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56F8167 数据表(HTML) 166 Page - Freescale Semiconductor, Inc |
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166 / 184 page ![]() 56F8367 Technical Data, Rev. 7.0 166 Freescale Semiconductor Preliminary Part 11 Packaging Note: The 160 Map Ball Grid Array is not available in the 56F8167 device. 11.1 56F8367 Package and Pin-Out Information This section contains package and pin-out information for the 56F8367. This device comes in a 160-pin Low-profile Quad Flat Pack (LQFP) and 160 Map Ball Grid Array. Figure 11-1 shows the package lay-out for the 160-pin LQFP, and Figure 11-2 for the160 Map Ball Grid Array. Figure 11-5 shows the mechanical parameters for the LQFP package and Figure 11-3 for the MAPBGA, Table 11-1 lists the pin-out for the 160-pin LQFP and Table 11-2 lists the pin-out for the 160 MAPBGA. Figure 11-1 Top View, 56F8367 160-Pin LQFP Package VDD_IO VPP2 CLKO TXD0 RXD0 PHASEA1 PHASEB1 INDEX1 HOME1 A1 A2 A3 A4 A5 VCAP4 VDD_IO A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 VSS D7 D8 D9 VDD_IO D10 GPIOB0 GPIOB1 GPIOB2 GPIOB3 Pin 1 Orientation Mark 121 41 GPIOB4 PWMB0 PWMB1 PWMB2 ANB4 ANB3 ANB2 ANB1 ANB0 VSSA_ADC VDDA_ADC VREFH VREFP VREFMID VREFN VREFLO TEMP_SENSE ANA7 ANA6 ANA5 ANA4 ANA3 ANA2 ANA1 ANA0 CLKMODE RESET RSTO VDD_IO VCAP3 EXTAL XTAL VDDA_OSC_PLL OCR_DIS D6 D5 D4 FAULTA3 D3 FAULTA2 FAULTA1 D2 FAULTA0 PWMA5 81 * When the on-chip regulator is disabled, these four pins become 2.5V VDD_CORE. |
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