56F8167 datasheet(178/184 Pages) FREESCALE

178 / 184 page

56F8367 Technical Data, Rev. 7.0

178

Freescale Semiconductor

Preliminary

The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T

thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so

that the thermocouple junction rests on the package. A small amount of epoxy is placed over the

thermocouple junction and over about 1mm of wire extending from the junction. The thermocouple wire

is placed flat against the package case to avoid measurement errors caused by cooling effects of the

thermocouple wire.

When heat sink is used, the junction temperature is determined from a thermocouple inserted at the

interface between the case of the package and the interface material. A clearance slot or hole is normally

required in the heat sink. Minimizing the size of the clearance is important to minimize the change in

thermal performance caused by removing part of the thermal interface to the heat sink. Because of the

experimental difficulties with this technique, many engineers measure the heat sink temperature and then

back-calculate the case temperature using a separate measurement of the thermal resistance of the

interface. From this case temperature, the junction temperature is determined from the junction-to-case

thermal resistance.

12.2 Electrical Design Considerations

Use the following list of considerations to assure correct operation:

•

Provide a low-impedance path from the board power supply to each VDD pin on the hybrid controller, and

from the board ground to each VSS (GND) pin

•

The minimum bypass requirement is to place six 0.01–0.1

µF capacitors positioned as close as possible to

the package supply pins. The recommended bypass configuration is to place one bypass capacitor on each

of the VDD/VSS pairs, including VDDA/VSSA. Ceramic and tantalum capacitors tend to provide better

performance tolerances.

•

Ensure that capacitor leads and associated printed circuit traces that connect to the chip VDD and VSS (GND)

pins are less than 0.5 inch per capacitor lead

•

Use at least a four-layer Printed Circuit Board (PCB) with two inner layers for VDD and VSS

•

Bypass the VDD and VSS layers of the PCB with approximately 100µF, preferably with a high-grade

capacitor such as a tantalum capacitor

•

Because the device’s output signals have fast rise and fall times, PCB trace lengths should be minimal

CAUTION

This device contains protective circuitry to guard

against damage due to high static voltage or electrical

fields. However, normal precautions are advised to

avoid

application

any

voltages

higher

than

maximum-rated voltages to this high-impedance circuit.

Reliability of operation is enhanced if unused inputs are

tied to an appropriate voltage level.

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