Block descriptions

STUSB4710

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DocID030499 Rev 4

3.6.3

VBUS power path assertion

directly or indirectly, through VBUS_EN_SRC pin.

The following table summarizes the configurations and the conditions that determine the

logic value of VBUS_EN_SRC pin during system operation.

Table 5: Conditions for VBUS power path assertion

Pin

Electrical

value

Operation conditions

Comment

Attached state

VBUS_EN_SRC

0

Attached.SRC

VDD > UVLO if

VDD_UVLO

enabled

and/or VDD <

OVLO if

VDD_OVLO

enabled

voltage range

if VBUS

_VALID_RANGE

enabled

VBUS

_VALID_RANGE

disabled

The signal is

asserted only if all

the valid operation

conditions are

met.

UnorientedDebug

Accessory.SRC

OrientedDebug

Accessory.SRC

HiZ

Any other state

VDD < UVLO if

VDD_UVLO

enabled

and/or VDD >

OVLO if

VDD_OVLO

enabled

voltage range

if VBUS

_VALID_RANGE

enabled

VBUS

_VALID_RANGE

disabled

The signal is de-

asserted when at

least one non-

valid operation

condition is met.

Activation of the UVLO and OVLO threshold detections can be done through NVM

programming (see Section 4: "User-defined startup configuration") and also by

UVLO and/or OVLO threshold detection is activated, the VBUS_EN_SRC pin is

3.7

High voltage protection

The STUSB4710 can be safely used in systems or connected to systems that handle high

that tolerates high voltage and ensures a protection up to 22 V in case of unexpected short

3.8

Hardware fault management

power path during system operation.

When such conditions occur, the circuit goes into a transient error recovery state named

ErrorRecovery in the Type-C FSM. When entering in this state, the device de-asserts the

VBUS power path by disabling the VBUS_EN_SRC pin, and it removes the terminations