MCP23008-ESLASHSS datasheet(4/40 Pages) MICROCHIP

4 / 40 page

MCP23008/MCP23S08

DS21919B-page 4

1.2

Power-on Reset (POR)

The on-chip POR circuit holds the device in reset until

VDD has reached a high enough voltage to deactivate

the POR circuit (i.e., release the device from reset).

The maximum VDD rise time is specified in Section 2.0

“Electrical Characteristics”.

When the device exits the POR condition (releases

reset), device operating parameters (i.e., voltage,

temperature, serial bus frequency, etc.) must be met to

ensure proper operation.

1.3

Serial Interface

This block handles the functionality of the I2C

(MCP23008) or SPI (MCP23S08) interface protocol.

The MCP23X08 contains eleven registers that can be

addressed through the serial interface block (Table 1-2):

TABLE 1-2:

1.3.1

SEQUENTIAL OPERATION BIT

The Sequential Operation (SEQOP) bit (IOCON

The address pointer can either be enabled (default) to

allow the address pointer to increment automatically

after each data transfer, or it can be disabled.

When

operating

Sequential

mode

(IOCON.SEQOP = 0), the address pointer automati-

cally increments to the next address after each byte

is clocked.

When operating in Byte mode (IOCON.SEQOP = 1),

the MCP23X08 does not increment its address

counter after each byte during the data transfer. This

gives the ability to continually read the same address

by providing extra clocks (without additional control

bytes). This is useful for polling the GPIO register for

data changes.

1.3.2

I2C™ INTERFACE

1.3.2.1

I2C Write Operation

The I2C Write operation includes the control byte and

Figure 1-1. This sequence is followed by eight bits of

data from the master and an Acknowledge (ACK) from

the MCP23008. The operation is ended with a STOP

or RESTART condition being generated by the master.

Data is written to the MCP23008 after every byte

transfer. If a STOP or RESTART condition is

generated during a data transfer, the data will not be

written to the MCP23008.

Byte writes and sequential writes are both supported

by the MCP23008. The MCP23008 increments its

address counter after each ACK during the data

transfer.

1.3.2.2

I2C Read Operation

The I2C Read operation includes the control byte

sequence, as shown in the bottom of Figure 1-1. This

sequence is followed by another control byte (includ-

ing the START condition and ACK) with the R/W bit

equal to a logic 1 (R/W = 1). The MCP23008 then

transmits the data contained in the addressed register.

The sequence is ended with the master generating a

STOP or RESTART condition.

1.3.2.3

I2C Sequential Write/Read

For sequential operations (Write or Read), instead of

transmitting a STOP or RESTART condition after the

data transfer, the master clocks the next byte pointed to

by the address pointer (see Section 1.3.1 “Sequential

Operation Bit”

for details

regarding

sequential

operation control).

The sequence ends with the master sending a STOP or

RESTART condition.

The MCP23008 address pointer will roll over to

address zero after reaching the last register address.

Refer to Figure 1-1.

1.3.3

SPI™ INTERFACE

1.3.3.1

SPI Write Operation

The SPI Write operation is started by lowering CS. The

Write command (slave address with R/W bit cleared) is

then clocked into the device. The opcode is followed by

an address and at least one data byte.

1.3.3.2

SPI Read Operation

The SPI Read operation is started by lowering CS. The

SPI read command (slave address with R/W bit set) is

then clocked into the device. The opcode is followed by

an address, with at least one data byte being clocked

out of the device.

Address

Access to:

00h

IODIR

01h

IPOL

02h

GPINTEN

03h

DEFVAL

04h

INTCON

05h

IOCON

06h

GPPU

07h

INTF

08h

INTCAP (Read-only)

09h

GPIO

0Ah

OLAT

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