CS61880 datasheet(3/70 Pages) CIRRUS

3 / 70 page

CS61880

DS450PP3

10. RECEIVER ............................................................................................................................ 26

10.1 Bipolar Output Mode ...................................................................................................... 26

10.2 Unipolar Output Mode ................................................................................................... 26

10.3 RZ Output Mode ............................................................................................................26

10.4 Receiver Powerdown/High-Z ......................................................................................... 27

10.5 Loss-of-Signal (LOS) ..................................................................................................... 27

10.6 Alarm Indication Signal (AIS) ......................................................................................... 27

11. JITTER ATTENUATOR ........................................................................................................ 28

12. OPERATIONAL SUMMARY ................................................................................................ 29

12.1 Loopbacks ..................................................................................................................... 29

12.2 Analog Loopback ...........................................................................................................29

12.3 Digital Loopback ............................................................................................................ 30

12.4 Remote Loopback ......................................................................................................... 30

13. HOST MODE ........................................................................................................................ 32

13.1 SOFTWARE RESET ..................................................................................................... 32

13.2 Serial Port Operation .....................................................................................................32

13.3 Parallel Port Operation .................................................................................................. 33

13.4 Register Set ................................................................................................................... 34

14. REGISTER DESCRIPTIONS ................................................................................................ 35

14.1 Revision/IDcode Register (00h) ..................................................................................... 35

14.2 Analog Loopback Register (01h) ................................................................................... 35

14.3 Remote Loopback Register (02h) .................................................................................. 35

14.4 TAOS Enable Register (03h) ......................................................................................... 35

14.5 LOS Status Register (04h) ............................................................................................ 35

14.6 DFM Status Register (05h) ............................................................................................ 35

14.7 LOS Interrupt Enable Register (06h) ............................................................................. 36

14.8 DFM Interrupt Enable Register (07h) ............................................................................ 36

14.9 LOS Interrupt Status Register (08h) .............................................................................. 36

14.10 DFM Interrupt Status Register (09h) ........................................................................... 36

14.11 Software Reset Register (0Ah) .................................................................................... 36

14.12 Performance Monitor Register (0Bh) ........................................................................... 36

14.13 Digital Loopback Reset Register (0Ch) ....................................................................... 36

14.14 LOS/AIS Mode Enable Register (0Dh) ........................................................................ 37

14.15 Automatic TAOS Register (0Eh) .................................................................................. 37

14.16 Global Control Register (0Fh) ...................................................................................... 37

14.17 Line Length Channel ID Register (10h) ....................................................................... 38

14.18 Line Length Data Register (11h) ................................................................................. 38

14.19 Output Disable Register (12h) ..................................................................................... 38

14.20 AIS Status Register (13h) ............................................................................................ 38

14.21 AIS Interrupt Enable Register (14h) ............................................................................ 39

14.22 AIS Interrupt Status Register (15h) ............................................................................. 39

14.23 AWG Broadcast Register (16h) ................................................................................... 39

14.24 AWG Phase Address Register (17h) ........................................................................... 39

14.25 AWG Phase Data Register (18h) ................................................................................ 39

14.26 AWG Enable Register (19h) ........................................................................................ 40

14.27 Reserved Register (1Ah) ............................................................................................. 40

14.28 Reserved Register (1Bh) ............................................................................................. 40

14.29 Reserved Register (1Ch) ............................................................................................. 40

14.30 Reserved Register (1Dh) ............................................................................................. 40

14.31 Bits Clock Enable Register (1Eh) ................................................................................ 40

14.32 Reserved Register (1Fh) ............................................................................................. 40

14.33 Status Registers .......................................................................................................... 40

14.33.1 Interrupt Enable Registers .............................................................................. 41

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