7

CAT5259

Document No. 2000, Rev. F

ACKNOWLEDGE

1

START

SCL FROM

MASTER

89

DATA OUTPUT

FROM TRANSMITTER

DATA OUTPUT

FROM RECEIVER

Figure 4. Acknowledge Condition

Figure 5. Slave Address Bits

0

1

0

1

A3A2A1

A0

CAT5259

*

A0, A1, A2 and A3 correspond to pin A0, A1, A2 and A3 of the device.

**

A0, A1, A2 and A3 must compare to its corresponding hard wired input pins.

Figure 3. Start/Stop Condition

START CONDITION

SDA

STOP CONDITION

SCL

tWR

STOP

CONDITION

START

CONDITION

ADDRESS

ACK

8TH BIT

BYTE n

SCL

SDA

Figure 2. Write Cycle Timing