8

CAT5259

Document No. 2000, Rev. F

INSTRUCTION AND REGISTER

DESCRIPTION

SLAVE ADDRESS BYTE

The first byte sent to the CAT5259 from the master/

processor is called the Slave/DPP Address Byte. The

most significant four bits of the slave address are a

device type identifier. These bits for the CAT5259 are

fixed at 0101[B] (refer to Table 1).

The next four bits, A3 - A0, are the internal slave address

and must match the physical device address which is

defined by the state of the A3 - A0 input pins for the

CAT5259 to successfully continue the command

sequence. Only the device which slave address matches

the incoming device address sent by the master executes

the instruction. The A3 - A0 inputs can be actively driven

INSTRUCTION BYTE

The next byte sent to the CAT5259 contains the instruction

and register pointer information. The four most significant

bits used provide the instruction opcode I3 - I0. The R1

and R0 bits point to one of the four data registers of each

associated potentiometer. The least two significant bits

point to one of four Wiper Control Registers. The format

is shown in Table 2.

Table 1. Identification Byte Format

ID3

ID2

ID1

ID0

A3

A2

A1

A0

0101

(MSB)

(LSB)

Device Type

Identifier

Slave Address

Table 2. Instruction Byte Format

I3

I2

I1

I0

R1

R0

P1

P0

(MSB)

(LSB)

Instruction

Data Register

WCR/Pot Selection

Opcode

Selection

Data Register Selected

R1

R0

DR0

0

0

DR1

0

1

DR2

1

0

DR3

1

1

Data Register Selection

Figure 6. Write Timing

5020 FHD F08

S

A

C

K

A

C

K

DR1 WCRDATA

S

T

O

P

P

BUS ACTIVITY:

MASTER

SDA LINE

S

T

A

R

T

A

C

K

SLAVE/DPP

ADDRESS

INSTRUCTION

BYTE

Fixed

Variable

op code

Register

Address

Pot1 WCR

Address