HPC-DEV-WDBC datasheet(22/30 Pages) NSC

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Design Considerations

Designs using the HPC family of 16-bit high speed CMOS

microcontrollers need to follow some general guidelines on

usage and board layout

Floating inputs are a frequently overlooked problem CMOS

inputs have extremely high impedance and if left open can

float to any voltage possibly causing internal devices to go

into active mode and draw DC current You should thus tie

unused inputs to VCC or ground either through a resistor or

directly Unlike the inputs unused outputs should be left

floating to allow the output to switch without drawing any DC

current

To reduce voltage transients keep the supply line’s parasit-

ic inductances as low as possible by reducing trace lengths

using wide traces ground planes and by decoupling the

supply with bypass capacitors In order to prevent additional

voltage spiking this local bypass capacitor must exhibit low

inductive reactance You should therefore use high frequen-

cy ceramic capacitors and place them very near the IC to

minimize wiring inductance

Keep VCC bus routing short When using double sided or

multilayer circuit boards use ground plane techniques

Keep ground lines short and on PC boards make them

as wide as possible even if trace width varies Use sepa-

rate ground traces to supply high current devices such as

relay and transmission line drivers

In systems mixing linear and logic functions and where

supply noise is critical to the analog components’ per-

formance provide separate supply buses or even sepa-

rate supplies

When using local regulators bypass their inputs with a

tantalum capacitor of at least 1 mF and bypass their out-

puts with a 10 mFto50 mF tantalum or aluminum electro-

lytic capacitor

If the system uses a centralized regulated power supply

usea10 mFto20 mF tantalum electrolytic capacitor or a

50 mFto100 mF aluminum electrolytic capacitor to de-

couple the VCC bus connected to the circuit board

Provide localized decoupling For random logic a rule

thumb

dictates

approximately

(spaced

within 12 cm) per every two to five packages and 100 nF

for every 10 packages You can group these capacitanc-

es but it’s more effective to distribute them among the

ICs If the design has a fair amount of synchronous logic

with outputs that tend to switch simultaneously addition-

al decoupling might be advisable Octal flip-flop and buff-

ers in bus-oriented circuits might also require more de-

coupling Note that wire-wrapped circuits can require

more decoupling than ground plane or multilayer PC

boards

A recommended crystal oscillator circuit to be used with the

HPC is shown in

Figure 20 See table for recommended

component values The recommended values given in the

table below have yielded consistent results and are made to

match a crystal with a 20 pF load capacitance with some

small allowance for layout capacitance

A recommended layout for the oscillator network should be

as close to the processor as physically possible entirely

within 1

distance This is to reduce lead inductance from

long PC traces as well as interference from other compo-

nents and reduce trace capacitance The layout should

contain a large ground plane either on the top or bottom

surface of the board to provide signal shielding and a con-

venient location to ground both the HPC and the case of

the crystal

It is very critical to have an extremely clean power supply for

the HPC crystal oscillator Ideally one would like a VCC and

ground plane that provide low inductance power lines to the

chip The power planes in the PC board should be decou-

pled with three decoupling capacitors as close to the chip

as possible A 10 mF a 01 mF and a 0001 mF dipped mica

or ceramic cap mounted as close to the HPC as is physically

possible on the board using the shortest leads or surface

mount components This should provide a stable power

supply and noiseless ground plane which will vastly im-

prove the performance of the crystal oscillator network

HPC Oscillator Table

XTAL

Frequency

R1 (X)

(MHz)

1500

1200

910

750

600

470

390

300

220

180

RF e 33 MX

C1 e 27 pF

C2 e 33 pF

XTAL Specifications The crystal used was an M-TRON Industries MP-1 Se-

ries XTAL ‘‘AT’’ cut parallel resonant

CL e 18 pF

Series Resistance is

40X

10 MHz

600X

2 MHz

TLDD10422 – 29

FIGURE 20 Recommended Crystal Circuit

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