HPC-DEV-WDBC datasheet(23/30 Pages) NSC

23 / 30 page

HPC46400E CPU

The HPC46400E CPU has a 16-bit ALU and six 16-bit regis-

ters

Arithmetic Logic Unit (ALU)

The ALU is 16 bits wide and can do 16-bit add subtract and

shift or logic AND OR and exclusive OR in one timing cycle

The ALU can also output the carry bit to a 1-bit C register

Accumulator (A) Register

The 16-bit A register is the source and destination register

for most IO arithmetic logic and data memory access op-

erations

Address (B and X) Registers

The 16-bit B and X registers can be used for indirect ad-

dressing They can automatically count up or down to se-

quence through data memory

Boundary (K) Register

The 16-bit K register is used to set limits in repetitive loops

of code as register B sequences through data memory

Stack Pointer (SP) Register

The 16-bit SP register is the stack pointer that addresses

the stack The SP register is incremented by two for each

push or call and decremented by two for each pop or return

The stack can be placed anywhere in user memory and be

as deep as the available memory permits

Program (PC) Register

The 16-bit PC register addresses program memory

Addressing Modes

ADDRESSING MODESACCUMULATOR AS

DESTINATION

This

the

‘‘normal’’

mode

addressing

for

the

HPC46400E (instructions are single-byte) The operand is

the memory addressed by the B register (or X register for

some instructions)

Direct

The instruction contains an 8-bit or 16-bit address field that

directly points to the memory for the operand

Indirect

The instruction contains an 8-bit address field The contents

of the WORD addressed points to the memory for the oper-

and

Indexed

The instruction contains an 8-bit address field and an 8- or

16-bit displacement field The contents of the WORD ad-

dressed is added to the displacement to get the address of

the operand

Immediate

The instruction contains an 8-bit or 16-bit immediate field

that is used as the operand

The operand is the memory addressed by the X register

This mode automatically increments or decrements the X

Conditional Skip

The operand is the memory addressed by the B register

This mode automatically increments or decrements the B

then compared with the K register A skip condition is gener-

ated if B goes past K

ADDRESSING MODESDIRECT MEMORY AS

DESTINATION

Direct Memory to Direct Memory

The instruction contains two 8- or 16-bit address fields One

field directly points to the source operand and the other field

directly points to the destination operand

Immediate to Direct Memory

The instruction contains an 8- or 16-bit address field and an

8- or 16-bit immediate field The immediate field is the oper-

and and the direct field is the destination

Double Register Indirect using the B and X Registers

Used only with Reset Set and IF bit instructions a specific

bit within the 64 kbyte address range is addressed using the

B and X registers The address of a byte of memory is

formed by adding the contents of the B register to the most

significant 13 bits of the X register The specific bit to be

modified or tested within the byte of memory is selected

using the least significant 3 bits of register X

HPC-DEV-WDBC 数据表(PDF) 23 Page - National Semiconductor (TI)

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