M95512-W, M95512-R

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Table 6. Protection Modes

Note: 1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in Table 6..

The Write Status Register (WRSR) instruction al-

lows the user to change the values of the Block

Protect (BP1, BP0) bits, to define the size of the

area that is to be treated as read-only, as defined

in Table 3..

The Write Status Register (WRSR) instruction also

allows the user to set or reset the Status Register

Write Disable (SRWD) bit in accordance with the

Write Protect (W) signal. The Status Register

Write Disable (SRWD) bit and Write Protect (W)

signal allow the device to be put in the Hardware

Protected Mode (HPM). The Write Status Register

(WRSR) instruction is not executed once the Hard-

ware Protected Mode (HPM) is entered.

The contents of the Status Register Write Disable

(SRWD) and Block Protect (BP1, BP0) bits are fro-

zen at their current values from just before the

start of the execution of Write Status Register

(WRSR) instruction. The new, updated, values

take effect at the moment of completion of the ex-

ecution of Write Status Register (WRSR) instruc-

tion.

The protection features of the device are summa-

rized in Table 4..

When the Status Register Write Disable (SRWD)

bit of the Status Register is 0 (its initial delivery

state), it is possible to write to the Status Register

provided that the Write Enable Latch (WEL) bit has

previously been set by a Write Enable (WREN) in-

struction, regardless of the whether Write Protect

(W) is driven High or Low.

When the Status Register Write Disable (SRWD)

bit of the Status Register is set to 1, two cases

need to be considered, depending on the state of

Write Protect (W):

–

If Write Protect (W) is driven High, it is

possible to write to the Status Register

provided that the Write Enable Latch (WEL) bit

has previously been set by a Write Enable

(WREN) instruction.

–

If Write Protect (W) is driven Low, it is not

possible to write to the Status Register even if

the Write Enable Latch (WEL) bit has

previously been set by a Write Enable

(WREN) instruction. (Attempts to write to the

Status Register are rejected, and are not

accepted for execution). As a consequence,

all the data bytes in the memory area that are

software protected (SPM) by the Block Protect

(BP1, BP0) bits of the Status Register, are

also hardware protected against data

modification.

Regardless of the order of the two events, the

Hardware Protected Mode (HPM) can be entered:

–

by setting the Status Register Write Disable

(SRWD) bit after driving Write Protect (W) Low

–

or by driving Write Protect (W) Low after

setting the Status Register Write Disable

(SRWD) bit.

The only way to exit the Hardware Protected Mode

(HPM) once entered is to pull Write Protect (W)

High.

If Write Protect (W) is permanently tied High, the

Hardware Protected Mode (HPM) can never be

activated, and only the Software Protected Mode

(SPM), using the Block Protect (BP1, BP0) bits of

the Status Register, can be used.

W

Signal

SRWD

Bit

Mode

Write Protection of the

Status Register

Memory Content

10

Software

Protected

(SPM)

Status Register is Writable

(if the WREN instruction

has set the WEL bit)

The values in the BP1 and

BP0 bits can be changed

Write Protected

Ready to accept Write

instructions

00

11

01

Hardware

Protected

(HPM)

Status Register is

Hardware write protected

The values in the BP1 and

BP0 bits cannot be

changed

Write Protected

Ready to accept Write

instructions