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High Speed CMOS Logic – 54HC74

Rev 1.0

21/11/17

LIMITS

PARAMETER

SYMBOL

CONDITIONS

25°C

85°C

FULL RANGE

4

UNITS

2.0

0.1

0.1

0.1

4.5

0.1

0.1

0.1

6.0

0.1

0.1

0.1

V

4.5

0.26

0.33

0.4

Maximum Low-Level

Output Voltage

6.0

0.26

0.33

0.4

V

Maximum Input

Leakage Current

6.0

±0.1

±1.0

±1.0

µA

Maximum Quiescent

Supply Current

6.0

2.0

20

80

µA

LIMITS

PARAMETER

SYMBOL

CONDITIONS

25°C

85°C

FULL RANGE

4

UNITS

2.0

6.0

4.8

4.0

4.5

30

24

20

Maximum Clock

Frequency

6.0

35

28

24

MHz

2.0

100

125

50

4.5

20

25

30

Propagation Delay,

CLK to Q or Q

(Figure 1)

6.0

17

21

26

ns

2.0

105

130

160

4.5

21

26

32

Propagation Delay,

PRE or CLR to Q or

Q (Figure 2)

6.0

18

22

27

ns

2.0

75

95

110

4.5

15

19

22

Output Transition

Time, Any Output

(Figure 1)

6.0

13

16

19

ns

Input Capacitance

-

10

10

10

pF

TYPICAL

Power Dissipation

Capacitance

(Per Flip-Flop)

-

39

pF

 

5. Not production tested in die form, characterized by chip design and tested in package.