DVSR CODEC
9
MX802
1998 MX-COM, Inc.
www.mxcom.com Tel: 800 638 5577 336 744 5050 Fax: 336 744 5054
Doc. # 20480033.008
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
All trademarks and service marks are held by their respective companies.
4.1.3
Speech
The CVSD encoder and decoder sampling rates are independently set via the Control Register (See Table 4,
Table 5, and Table 6) to 16, 25, 32, 50, and 64kbps. This allows the user to choose between speech quality
and storage time while providing for time compression or expansion of the speech signals.
The DVSR Codec can handle from 256kbits to 4Mbits of DRAM, giving, in the case of the 32kbps sampling
rate, from 8 to 131 seconds of speech storage.
For speech storage purposes, the memory is divided into ‘pages’ of 1024 bits each, corresponding to 32ms at
32kbps sampling rate.
A 256 kbit DRAM contains
256 ‘pages’
A 1 Mbit DRAM contains
1024 ‘pages’
A 4 Mbit DRAM contains
4096 ‘pages’
When used without DRAM, the decoder sampling rate (8-64kbps) is determined by an external clock source
applied to the Decoder Clock pin.
4.1.3.1
Store and Play Speech Commands
Speech storage and playback may take place simultaneously. These commands are transmitted, via C-BUS,
to the MX802 in the following form:
STORE OR PLAY “N” (1024-bit) PAGES (of decoded speech data) STARTING AT PAGE “N”.
“N” can be any number between 0 and F (1-16 pages). “X” can be any number from 405 (4Mbit DRAM), as
shown below. Preceded by A/C, this command writes 16 bits (byte 1 or byte0) of data from the
microcontroller to the Store or Play command Buffer.
MSB
BYTE 1
BYTE2
LSB
15
14
13
12
11
10
9
876543
21
0
N
X
4.1.3.2
Speech Store Commands
4.1.3.2.1
62H STORE “N” PAGES – START PAGE “X” (immediate)
63H STORE “N” PAGES – START PAGE “X” (buffered)
The digitized speech from the CVSD encoder is stored in consecutive DRAM locations with the Speech Store
Counters sequencing through the DRAM addresses and counting the number of complete pages stored since
the start of the execution of the command.
As soon as the command has terminated, the following events take place:
1.
The Store Command Complete bit in the Status Register (Table 7) is set.
2.
An Interrupt Request ( IRQ ) is sent, if enabled, to the microcontroller.
3.
The next speech storage command (if present) is immediately taken from the Store Command Buffer and
execution f the new command commences.
The IRQ output is cleared by reading the Status Register:
4.1.3.2.2
61H READ STATUS REGISTER (Table 8)
To provide continuity of speech commands, both Store and Play Commands can be presented to the MX802
in one of two formats: immediate or buffered.
An immediate command will be started on completion of its loading, irrespective of the condition of the current
command.
A buffered command will begin after the completion of the current Store or Play command, unless Speech
Synchronization Bits (Control Register) are set.
Buffering of commands lets the DVSR Codec execute a series of commands without intervening gaps even
though the microcontroller may take several milliseconds to respond to each “Command Complete” Interrupt
Request.
In either case, the Store or Play Command Complete bit of the status register will be cleared.
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