PM6685

3 Block & pin connection diagrams

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18

LDO5

5V internal regulator output. LDO5 pin supplies all gate drivers, the internal

circuitry and an external load. It can provide up to 100mA peak current.

19

VIN

Device input supply voltage. A bypass filter (4

Ω and 4.7 µF) between the battery

and this pin is recommended.

20

CSENSE5

Current sense input for the switching 5V section. This pin must be connected

threshold.

21

PHASE5

Switch node connection and return path for the high side driver for the 5V section.

22

HGATE5

High-side gate driver ouput for the 5V section.

23

BOOT5

Bootstrap capacitor connection for the switching 5V section. It supplies the high-

side gate driver.

24

SKIP

Pulse skipping mode control input. It is a three states pin.

If the pin is at its high level(e.g. cnnected to LDO5) the PWM mode is enabled.

If the pin is at its low level (e.g. connected to GND), the pulse skip mode is

enabled.

If the pin is at its middle level (e.g. connected to Vref) the pulse skip mode is

enabled but limiting the min frequency to 25KHz.

25

EN5

5V SMPS enable input. The 5V section is enabled appling a high logic level

(>2.4V) to this pin, while is disabled appling a low logic level (<0.8V). When the

section is disabled the High Side gate driver goes low and Low Side gate driver

goes high. If both EN3 and EN5 pins are low and SHDN pin is high the device

enters in standby mode.

26

PGOOD5

Power Good ouput signal for the 5V section. This pin is an open drain ouput.

The pin is pulled low if the output is disabled or is out of the specified window

(approximately +/- 10% of its nominal value).

27

PGOOD3

Power Good ouput signal for the 3.3V section. This pin is an open drain ouput.

The pin is pulled low if the output is disabled or is out of the specified window

(approximately +/- 10% of its nominal value).

28

LDP3SEL

Control pin for the 3.3V internal linear regulator. This pin determines three

operative modes for the LDO3.

If LDO3_SEL pin is at its low level the LDO3 is always OFF.

If LDO3_SEL pin is at its high level the LDO3 is always ON

If LDO3_SEL pin is connected to VREF and OUT3 is greater than the LDO3

bootstrap switch threshold, the LDO3 regulator shuts down and the LDO3 pin will

be directly connected to OUT3 through a 3 (max) switch.

29

OUT5

Output voltage sense for the 5V switching section.This pin must be directly

connected to the output voltage of the switching section.

30

COMP5

DC voltage error compensation pin for the 5V switching section.

31

Device Supply Voltage pin. Connect this pin to LDO5

32

VREF

High accuracy output voltage reference (1.237V). It can deliver 50uA. Bypass to

SGND with a 100nF capacitor.

Table 3.

Pin description