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CS6403 数据表(PDF) 2 Page - Cirrus Logic

部件名 CS6403
功能描述  Echo-Cancelling Codec
PDF  54 Pages
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制造商  CIRRUS [Cirrus Logic]
网页  http://www.cirrus.com
标志 CIRRUS - Cirrus Logic

CS6403 数据表(HTML) 2 Page - Cirrus Logic

  CS6403 Datasheet HTML 1Page - Cirrus Logic CS6403 Datasheet HTML 2Page - Cirrus Logic CS6403 Datasheet HTML 3Page - Cirrus Logic CS6403 Datasheet HTML 4Page - Cirrus Logic CS6403 Datasheet HTML 5Page - Cirrus Logic CS6403 Datasheet HTML 6Page - Cirrus Logic CS6403 Datasheet HTML 7Page - Cirrus Logic CS6403 Datasheet HTML 8Page - Cirrus Logic CS6403 Datasheet HTML 9Page - Cirrus Logic Next Button
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ADC CHARACTERISTICS (TA = 25 °C; All DVDD, AVDD, and PVDD = 5.0V, Digital Input Levels:
Logic 0 = 0V, Logic 1 = DVDD; Signal test frequency 1kHz, word rate (Fs) = 8kHz, audio signal measurement
bandwidth is 20Hz to 4kHz; Microphone amp gain = 0dB; SPRKOUT outputs connected to 8
Ω load; CLKIN fre-
quency = 8.192MHz; unless otherwise specified) Note 1.
Parameter
Symbol
Min
Typ
Max
Units
ADC Resolution With No Missing Codes
12
-
-
bits
Instantaneous Dynamic Range
IDR
67
72
-
dB
Total Harmonic Distortion at -0.5dBFS signal level
THD
-
0.01
0.05
%
Gain Drift
(Note 2)
-
150
-
ppm/°C
Offset Error
-
0
2
LSB
Full Scale Input Voltage
(Note 3)
0.85
1.0
1.1
Vp
Input Resistance
(at MICIN)
(Note 2)
25
-
-
k
Ω
Input Capacitance
(at MICIN)
(Note 2)
-
15
-
pF
Sample Rate
Fs
-
8
-
kHz
Microphone Amp Gain
(switchable on/off)
24
26
28
dB
Anti-aliasing Rejection
-
30
-
dB
Power Supply Rejection
(1kHz)
PSR
40
-
-
dB
Frequency Response
-0.6
-
0.6
dB
Transition Band
0.45
-
0.6
Fs
Stop Band Rejection
70
-
-
dB
VREF Reference Voltage Output
-
2.0
-
V
VCM Voltage Output
constant load only, >100 k
Ω
-1.0
-
V
Group Delay
(Note 4)
-
1
-
ms
Group Delay Variations vs. Frequency
(Note 4)
-
0.0
-
µs
Notes:
1. Bench testing is done with Crystal part CXT8192 driving CLKIN, automated device testing utilizes
test system provided clock sources.
2. Guaranteed by design/characterization.
3. This is the peak input voltage (in volts) with the mic amp gain set to 0 dB. Peak-to-peak voltage is
2x peak. Input signals will be properly clipped if the peak signal is greater than full scale, but less
than 2x full scale.
4. This group-delay specification is for the ADC only; additional group delay is introduced by the
AGC and high-pass filter that is implemented on the CS6403 in software.
CS6403
2
DS192PP6



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