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CS42418 数据表(PDF) 39 Page - Cirrus Logic

部件名 CS42418
功能描述  110 dB, 192kHz 8-Ch CODEC WITH PLL
PDF  67 Pages
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制造商  CIRRUS [Cirrus Logic]
网页  http://www.cirrus.com
标志 CIRRUS - Cirrus Logic

CS42418 数据表(HTML) 39 Page - Cirrus Logic

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CS42418
5.8
OMCK/PLL_CLK Ratio (address 07h) (Read Only)
5.8.1
OMCK/PLL_CLK RATIO (RATIOX)
Default = sixth
Function:
This register allows the user to find the exact absolute frequency of the recovered MCLK coming from
the PLL. This value is represented as an integer (RATIO7:6) and a fractional (RATIO5:0) part. For
example, an OMCK/PLL_CLK ratio of 1.5 would be displayed as 60h.
5.9
Clock Status (address 08h) (Read Only)
5.9.1
SYSTEM CLOCK SELECTION (ACTIVE_CLK)
Default = x
0 - Output of PLL
1 - OMCK
Function:
This bit identifies the source of the internal system clock (MCLK).
5.9.2
PLL CLOCK FREQUENCY (PLL_CLKX)
Default = xxxh
Function:
The CS42418 will auto-detect the ratio between the OMCK and the recovered clock from the PLL,
which is displayed in register 07h. Based on this ratio, the absolute frequency of the PLL clock can
be determined, and this information is displayed according to the following table. If the absolute fre-
quency of the PLL clock does not match one of the given frequencies, this register will display the
closest available value.
NOTE: These bits are set to ‘111’b when the FRC_PLL_LK bit is ‘1’b.
76543
210
RATIO7(21)RATIO6(20)RATIO5(2-1)RATIO4(2-2)RATIO3(2-3)RATIO2(2-4)RATIO1(2-5)RATIO0(2-6)
76543
210
Reserved
Reserved
Reserved
Reserved
Active_CLK
PLL_CLK2
PLL_CLK1
PLL_CLK0
PLL_CLK2
PLL_CLK1
PLL_CLK0
Description
00
0
8.1920 MHz
00
1
11.2896 MHz
01
0
12.288 MHz
01
1
16.3840 MHz
10
0
22.5792 MHz
10
1
24.5760 MHz
11
0
45.1584 MHz
11
1
49.1520 MHz
Table 13. PLL Clock Frequency Detection



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