| 数据搜索系统,热门电子元器件搜索 |
|
CS61310 数据表(PDF) 21 Page - Cirrus Logic |
|
|
|||||||||||||||||||||||||||||
CS61310 数据表(HTML) 21 Page - Cirrus Logic |
|
21 / 30 page ![]() CS61310 DS440F1 FEB ‘03 21 Power Supplies TGND - Ground Transmit Driver, Pin 14. Power supply ground for the transmit driver; typically 0 Volts. TV+ - Power Supply, Transmit Driver, Pin 15. Power supply for the transmit driver; typically +5 Volts. RV+ - Power Supply, Pin 21. Power supply for all subcircuits except the transmit driver; typically +5 Volts. RGND - Ground, Pin 22. Power supply ground for all subcircuits except the transmit driver; typically 0 Volts. Oscillator XTALIN, XTALOUT - Crystal Connections, Pins 9 and 10. A 6.176 MHz crystal can be connected across these pins. This oscillator provides the reference frequency for the LIU if MCLK is not provided. The load capacitance presented to the crystal by these pins should be approximately 19pF (IC and package, when soldered into a circuit board). The jitter attenuator may be disabled by tying XTALIN to RV+ through a 1k Ω resistor, and floating XTALOUT. When pin 9 has no clock input, a clock must be supplied to the MCLK pin. Alternatively an external 6.176 MHz clock can be driven into XTALIN, and the jitter attenuator circuit will operate. If MCLK is provided, and XTALIN is tied low or left floating, the jitter attenuator will be enabled. Control MCLK - Master Clock Input, Pin 1. Either MCLK or the crystal oscillator provide the master frequency reference for the CS61310. If both MCLK and the crystal oscillator are present, the oscillator is ignored. MCLK should be 1.544 MHz. If MCLK is not used, it must be grounded. MODE - Mode Select Input, Pin 5. Setting the MODE pin high puts the CS61310 into Host Mode where the device is controlled by a microprocessor, via a serial port. Setting the MODE pin low, configures the part for hardware mode control where various control and status are provided on dedicated pins. The MODE pin is internally pulled down placing the part in Hardware Mode when this pin is left floating. Tying the MODE pin to RCLK places the chip in Hardware Mode and enables the B8ZS encoder/decoder (provided that coder mode has been enabled; see the description for TNEG/UBS pin). JASEL - Jitter Attenuator Select, Pin 11. If the jitter attenuator is enabled (crystal oscillator active, or XTALIN tied low or left floating with MCLK provided), setting JASEL high places the jitter attenuator in the receive path; setting JASEL low places the jitter attenuator in the transmit path. NC - No Connect, Pin 17. The input voltage to this pin does not effect normal operation. |
|
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |