数据搜索系统，热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

预览 PDF HTML

CS61583 数据表(PDF) 6 Page - Cirrus Logic

部件名 CS61583
功能描述  DUAL T1/E1 LINE INTERFACE
PDF  44 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  CIRRUS [Cirrus Logic]
网页  http://www.cirrus.com
标志 CIRRUS - Cirrus Logic

CS61583 数据表(HTML) 6 Page - Cirrus Logic

Back Button CS61583 Datasheet HTML 2Page - Cirrus Logic CS61583 Datasheet HTML 3Page - Cirrus Logic CS61583 Datasheet HTML 4Page - Cirrus Logic CS61583 Datasheet HTML 5Page - Cirrus Logic CS61583 Datasheet HTML 6Page - Cirrus Logic CS61583 Datasheet HTML 7Page - Cirrus Logic CS61583 Datasheet HTML 8Page - Cirrus Logic CS61583 Datasheet HTML 9Page - Cirrus Logic CS61583 Datasheet HTML 10Page - Cirrus Logic Next Button
Zoom Inzoom in Zoom Outzoom out
 6 / 44 page
background image
SWITCHING CHARACTERISTICS - T1 CLOCK/DATA (TA = -40 to 85 °C; power supply
pins within
±5% of nominal; Inputs: Logic 0 = 0V, Logic 1 = DV+) (See Figures 1, 2, and 3)
Parameter
Symbol
Min
Typ
Max
Units
TCLK Frequency
(Note 25)
ftclk
-
1.544
-
MHz
TCLK Duty Cycle
tpwh2/tpw2
30
50
70
%
RCLK Duty Cycle
(Note 26) tpwh1/tpw1
45
50
55
%
Rise Time (All Digital Outputs)
(Note 27)
tr
-
-
65
ns
Fall Time (All Digital Outputs)
(Note 27)
tf
-
-
65
ns
RPOS/RNEG (RDATA) to RCLK Rising Setup Time
tsu1
-
274
-
ns
RCLK Rising to RPOS/RNEG (RDATA) Hold Time
th1
-
274
-
ns
TPOS/TNEG (TDATA) to TCLK Falling Setup Time
tsu2
25
-
-
ns
TCLK Falling to TPOS/TNEG (TDATA) Hold Time
th2
25
-
-
ns
Notes: 25. The maximum burst rate of a gapped TCLK input clock is 8.192 MHz. For the gapped clock to be
tolerated by the CS61583, the jitter attenuator must be switched to the transmit path of the line
interface. The maximum gap size that can be tolerated on TCLK is 28 UIp-p.
26. RCLK duty cycle may be outside the specified limits when the jitter attenuator is in the receive path,
and when the jitter attenuator is employing the overflow/underflow protection mechanism.
27. At max load of 50 pF.
SWITCHING CHARACTERISTICS - E1 CLOCK/DATA (TA = -40 to 85 °C; power supply
pins within
±5% of nominal; Inputs: Logic 0 = 0V, Logic 1 = DV+) (See Figures 1, 2, and 3)
Parameter
Symbol
Min
Typ
Max
Units
TCLK Frequency
(Note 25)
ftclk
-
2.048
-
MHz
TCLK Duty Cycle
tpwh2/tpw2
30
50
70
%
RCLK Duty Cycle
(Note 26) tpwh1/tpw1
45
50
55
%
Rise Time (All Digital Outputs)
(Note 27)
tr
-
-
65
ns
Fall Time (All Digital Outputs)
(Note 27)
tf
-
-
65
ns
RPOS/RNEG (RDATA) to RCLK Rising Setup Time
tsu1
-
194
-
ns
RCLK Rising to RPOS/RNEG (RDATA) Hold Time
th1
-
194
-
ns
TPOS/TNEG (TDATA) to TCLK Falling Setup Time
tsu2
25
-
-
ns
TCLK Falling to TPOS/TNEG (TDATA) Hold Time
th2
25
-
-
ns
CS61583
6
DS172PP5



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com