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CS61584A 数据表(PDF) 8 Page - Cirrus Logic

部件名 CS61584A
功能描述  DUAL T1/E1 LINE INTERFACE
PDF  54 Pages
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制造商  CIRRUS [Cirrus Logic]
网页  http://www.cirrus.com
标志 CIRRUS - Cirrus Logic

CS61584A 数据表(HTML) 8 Page - Cirrus Logic

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CS61584A
8
DS261PP5
DS261PP5
DIGITAL CHARACTERISTICS (T
A = -40 to 85 °C; power supply pins within ±5% of nominal.)
Notes: 23. Digital inputs are designed for CMOS logic levels.
24. Digital outputs are TTL compatible and drive CMOS levels into a CMOS load.
SWITCHING CHARACTERISTICS (T
A = -40 to 85 °C; power supply pins within ±5% of nominal;
Inputs: Logic 0 = 0 V, Logic 1 = DV+.)
Notes: 25. The maximum burst rate of a gapped TCLK input clock is 8.192 MHz. For the gapped clock to be
tolerated by the CS61584A, the jitter attenuator must be switched to the transmit path of the line
interface. The maximum gap size that can be tolerated on TCLK is 28 UIp-p.
26. RCLK duty cycle may be outside the specified limits when the jitter attenuator is in the transmit path
and when the jitter attenuator is employing the overflow/underflow protection mechanism.
27. At max load of 50 pF.
Parameter
Symbol
Min
Max
Unit
High-Level Input Voltage
(Note 23)
VIH
(DV+) - 0.5
-
V
Low-Level Input Voltage
(Note 23)
VIL
-0.5
V
High-Level Output Voltage (Iout = -40 µA)
(Note 24)
VOH
(DV+) - 0.3
-
V
Low-Level Output Voltage (Iout = 1.6 mA)
(Note 24)
VOL
-0.3
V
Input Leakage Current (Digital pins except J-TMS and J-TDI)
-
±10
µA
Parameter
Symbol
Min
Typ
Max
Unit
T1 Clock/Data
TCLK Frequency
(Note 25)
ftclk
-1.544
-
MHz
TCLK Duty Cycle
tpwh2/tpw2
20
50
80
%
RCLK Duty Cycle
(Note 26)
tpwh1/tpw1
45
50
55
%
Rise Time (All Digital Outputs)
(Note 27)
tr
-
-
65
ns
Fall Time (All Digital Outputs)
(Note 27)
tf
-
-
65
ns
RPOS/RNEG (RDATA) to RCLK Rising Setup Time
tsu1
-274
-
ns
RCLK Rising to RPOS/RNEG (RDATA) Hold Time
th1
-274
-
ns
TPOS/TNEG (TDATA) to TCLK Falling Setup Time
tsu2
25
-
-
ns
TCLK Falling to TPOS/TNEG (TDATA) Hold Time
th2
25
-
-
ns
E1 Clock/Data
TCLK Frequency
(Note 25)
ftclk
-2.048
-
MHz
TCLK Duty Cycle
tpwh2/tpw2
20
50
80
%
RCLK Duty Cycle
(Note 26)
tpwh1/tpw1
45
50
55
%
Rise Time (All Digital Outputs)
(Note 27)
tr
-
-
65
ns
Fall Time (All Digital Outputs)
(Note 27)
tf
-
-
65
ns
RPOS/RNEG (RDATA) to RCLK Rising Setup Time
tsu1
-194
-
ns
RCLK Rising to RPOS/RNEG (RDATA) Hold Time
th1
-194
-
ns
TPOS/TNEG (TDATA) to TCLK Falling Setup Time
tsu2
25
-
-
ns
TCLK Falling to TPOS/TNEG (TDATA) Hold Time
th2
25
-
-
ns
CS61584A
8
DS261F1



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