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CS61584A 数据表(PDF) 36 Page - Cirrus Logic |
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CS61584A 数据表(HTML) 36 Page - Cirrus Logic |
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36 / 54 page ![]() CS61584A 36 DS261PP5 DS261PP5 10.16 Exit1-IR State This is a temporary state. While in this state, if J- TMS is held high, a rising edge applied to J-TCK causes the controller to enter the Update-IR state, which terminates the scanning process. If J-TMS is held low and a rising edge is applied to J-TCK, the controller enters the Pause-IR state. The test data register selected by the current instruction retains its previous value and the instruction does not change during this state. 10.17 Pause-IR State The pause state allows the test controller to tempo- rarily halt the shifting of data through the instruc- tion register. The test data register selected by the current instruction retains its previous value and the instruction does not change during this state. The controller remains in this state as long as J- TMS is low. When J-TMS goes high and a rising edge is applied to J-TCK, the controller moves to the Exit2-IR state. 10.18 Exit2-IR State This is a temporary state. While in this state, if J- TMS is held high, a rising edge applied to J-TCK causes the controller to enter the Update-IR state, which terminates the scanning process. If J-TMS is held low and a rising edge is applied to J-TCK, the controller enters the Shift-IR state. The test data register selected by the current in- struction retains its previous value and the instruc- tion does not change during this state. 10.19 Update-IR State The instruction shifted into the instruction register is latched into the parallel output from the shift-reg- ister path on the falling edge of J-TCK. When the new instruction has been latched, it becomes the current instruction. The test data registers selected by the current instruction retain their previous val- ue. 10.20 JTAG Application Examples Figures 25 and 26 illustrate examples of updating the instruction and data registers during JTAG op- eration. CS61584A 36 DS261F1 |
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