ST92195C datasheet(59/249 Pages) STMICROELECTRONICS

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ST92195C/D - INTERRUPTS

INTERRUPT REGISTERS (Cont’d)

EXTERNAL MEMORY REGISTER 2 (EMR2)

R246 - Read/Write

Reset value: 0000 1111 (0Fh)

Bits 7, 5:0 = Reserved, keep in reset state. Refer

to the external Memory Interface Chapter.

Bit 6 = ENCSR:

Enable Code Segment Register.

This bit is set and cleared by software. It affects

the ST9 CPU behaviour whenever an interrupt re-

quest is issued.

0: The CPU works in original ST9 compatibility

mode. For the duration of the interrupt service

routine, ISR is used instead of CSR, and the in-

terrupt stack frame is identical to that of the orig-

inal ST9: only the PC and Flags are pushed.

This avoids saving the CSR on the stack in the

event of an interrupt, thus ensuring a faster in-

terrupt response time. The drawback is that it is

not possible for an interrupt service routine to

perform inter-segment calls or jumps: these in-

structions would update the CSR, which, in this

case, is not used (ISR is used instead). The

code segment size for all interrupt service rou-

tines is thus limited to 64K bytes.

1: ISR is only used to point to the interrupt vector

table and to initialize the CSR at the beginning

of the interrupt service routine: the old CSR is

pushed onto the stack together with the PC and

flags, and CSR is then loaded with the contents

of ISR. In this case, iret will also restore CSR

from the stack. This approach allows interrupt

service routines to access the entire 4 Mbytes of

address space; the drawback is that the inter-

rupt response time is slightly increased, be-

cause of the need to also save CSR on the

stack. Full compatibility with the original ST9 is

lost in this case, because the interrupt stack

frame is different; this difference, however,

should not affect the vast majority of programs.

ENCSR

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