ST92195C datasheet(87/249 Pages) STMICROELECTRONICS

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ST92195C/D - TELETEXT DISPLAY STORAGE RAM INTERFACE

TDSRAM (Cont’d)

7.3.2 Functional Description

The Teletext Data Storage RAM Interface (TRI)

manages the data flows between the different sub-

units (display, acquisition, 40-byte buffer, CPU in-

terface) and the internal RAM. A specific set of

buses (8 bit data TRIDbus, 13 bit address TRIA-

bus) is dedicated to these data flows.

As this TDSRAM interface has to manage TV ori-

ented real time signals (On-Screen-Display, Tele-

text slicing storage):

– Its timing generator uses the same frequency

generator as for the Display (Pixel frequency

multiplier),

– Its controller is hardware synchronized to the ba-

sic horizontal and vertical sync signals got

through the CSYNC Controller,

– Its architecture gives priority to the TV real time

constraints: whenever there is any access con-

tention between the CPU (only in case of direct

CPU access) and one of the hardware units, the

CPU automatically enters a "wait" configuration

until its request is serviced.

7.3.2.1 TV Line Timesharing

During a TV line, to maintain maximum perform-

ance, a continuous cycle is run repetitively. This

cycle is divided in 8 sub-cycles called "slots".

This 8-slot cycle is repeated continuously until the

next TV line-start occurs (horizontal sync pulse de-

tected). When a horizontal sync pulse is detected,

the running slot is completed and the current cycle

is broken.

The following naming convention is used: "ACQ"

stands for Acquisition storage slot, "CPU" stands

for direct CPU access slot, "DIS" stands for Dis-

play reading slot, "MBT" stands for multi-byte

transfer. Each slot represents a single byte ex-

change (read or write) between the TDSRAM

memory and the other units:

Acquisition Storage (ACQ). 1 byte issued from

the Teletext Acquisition unit written to the TD-

SRAM, the address is defined by the acquisition

address generator.

Display Reading (DIS). 1 byte is read from the

TDSRAM and sent to the display unit, the address

being defined by the display address generator.

Multi-Byte Transfer (MBT). 1 byte of the 40 bytes

Buffer is exchanged (read or written) between the

40-byte Buffer and the TDSRAM, the address be-

ing defined by the 40-byte buffer address genera-

tor.

CPU Access (CPU). 1 byte is exchanged (read or

written) between the TDSRAM and the CPU, the

address being defined by the CPU address bus.

7.3.2.2 TV Field Timesharing

The choice between Acquisition and Display cy-

cles is done automatically on a TV line basis.

The complete TV field start (VBI) is affected to Ac-

quisition cycles up to end of line 24. The rest of the

TV field is affected to Display cycles up to the next

field (next vertical sync pulse).

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