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TFP503PZP 数据表(PDF) 3 Page - Texas Instruments |
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TFP503PZP 数据表(HTML) 3 Page - Texas Instruments |
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3 / 27 page ![]() TFP503 PanelBus HDCP DIGITAL RECEIVER SLDS149 − AUGUST 2004 3 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 functional block diagram _ + Latch Channel 2 _ + Latch Channel 1 _ + Latch Channel 0 _ + PLL T.M.D.S. Decoder CH2[9:0] CH1[9:0] CH0[9:0] RED[7:0] CTL2 GRN[7:0] CTL1 BLU[7:0] VSYNC HSYNC QE[23:0] QO[23:0] ODCK DE SCDT CTL2 CTL1 VSYNC HSYNC 1.8 V Regulator 3.3 V Internal 50 Ω Termination Rx2+ Rx2- Rx1+ Rx1- Rx0+ Rx0- RxC+ RxC- HDCP Decryption RED[7:0] CTL2 GRN[7:0] CTL1 BLU[7:0] VSYNC HSYNC Panel Interface Encrypted Embedded HDCP Keys RCL 3.3 V RDA Key Decryption RAM Block I2C Slave I/F for DDC DDC_SCL DDC_SA DDC_SDA I2C Control Registers |
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