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A6801SEP 数据表(PDF) 3 Page - Allegro MicroSystems

部件名 A6801SEP
功能描述  DABiC-5 Latched Sink Drivers
PDF  12 Pages
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制造商  ALLEGRO [Allegro MicroSystems]
网页  http://www.allegromicro.com
标志 ALLEGRO - Allegro MicroSystems

A6801SEP 数据表(HTML) 3 Page - Allegro MicroSystems

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3
Worcester, Massachusetts 01615-0036 (508) 853-5000
115 Northeast Cutoff, Box 15036
www.allegromicro.com
A6800/A6801
DABiC-5 Latched Sink Drivers
ELECTRICAL CHARACTERISTICS1 Unless otherwise noted: TA = 25°C, logic supply operating voltage Vdd=3.0Vto5.5V
Characteristic
Symbol
Test Conditions
Vdd = 3.3V
Vdd = 5V
Units
Min.
Typ.
Max. Min.
Typ.
Max.
Output Leakage Current
ICEX
VOUT = 50 V
10
10
µA
Output Sustaining Voltage
VCE(SUS)
IOUT = 350 mA, L = 3 mH
35
35
V
Collector-Emitter Saturation
Voltage
VCE(SAT)
IOUT = 100 mA
0.8
1.0
0.8
1.0
V
IOUT = 200 mA
0.9
1.1
0.9
1.1
V
IOUT = 350 mA (See note 2)
1.0
1.3
1.0
1.3
V
Input Voltage
VIN(1)
2.2
3.3
V
VIN(0)
1.1
1.7
V
Input Resistance
RIN
50
50
kΩ
Logic Supply Current
IDD(1)
One output on, IOUT = 100 mA
1.0
1.0
mA
IDD(0)
All outputs off
130
150
130
150
µA
Clamp Diode Leakage Current
Ir
Vr= 50 V
50
50
µA
Clamp Diode Forward Voltage
Vf
If = 350 mA
2.0
2.0
V
Output Fall Time
tf
VCC = 50V, R1 = 500 Ω, C1≤30pF
–80–
–80–
ns
Output Rise Time
tr
VCC = 50V, R1 = 500 Ω, C1≤30pF
100
100
ns
1
Operation of these devices with standard TTL or DTL may require the use of appropriate pull-up resistors to ensure a minimum logic 1.
2
Because of limitations on package power dissipation, the simultaneous operation of multiple drivers can only be accomplished by reduction in duty cycle.
OUT N
INN
STR OB E
C L EAR
E NAB L E
t-1
t
0
100
X
OF F
1
100
X
ON
XX
1
X
X
OF F
XX
X
1
X
OF F
X
0
0
0
ON
ON
X0
0
0
OF F
OF F
X = irrelevant
t-1 = previous output state
t = present output state
OUTP UT
Truth Table



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