STM32MP151AAB3 datasheet(145/253 Pages) STMICROELECTRONICS

145 / 253 page

DS12500 Rev 3

145/253

STM32MP151A/D

Electrical characteristics

232

Figure 17. Low-speed external clock source AC timing diagram (analog bypass)

Low-speed external user clock generated from an external source

In bypass mode the LSE oscillator is switched off and the input pin is a standard I/O. The

external clock signal has to respect the Table 50: I/O static characteristics. However, the

recommended clock input waveform is shown in Figure 18 for digital bypass and Figure 17

for analog bypass.

Table 30. Low-speed external user clock characteristics

(analog bypass)(1)

1. Guaranteed by design.

Symbol

Parameter

Min

Typ

Max

Unit

fLSE_ext

User external clock source frequency

32.768

kHz

VLSE

Absolute input range

VSW(2)

2. VSW is equal to VDD when present or VBAT otherwise

VPP

OSC32_IN peak-to-peak amplitude

0.2(3)

3. Minimum peak-to-peak amplitude (@25 °C, 0.1 < VDC < VSW - 0.1 V) where VDC is the DC component of

the input signal.

I(LSE)

Power consumption

120

MSv63037V1

VLSE

TLSE

VPP

STM32

OSC32_IN

fLSE_ext

External

clock source

Table 31. Low-speed external user clock characteristics (digital bypass)(1)

Symbol

Parameter

Min

Typ

Max

Unit

fLSE_ext

User external clock source frequency

32.768

1000

kHz

VLSEH

OSC32_IN input pin high level voltage

0.7 × VDD

-VDD

VLSEL

OSC32_IN input pin low level voltage

VSS

0.3 VDD

tw(LSEH)

tw(LSEL)

OSC32_IN high or low time

250

1. Guaranteed by design.

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