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STM32MP151AAB3 数据表(PDF) 198 Page - STMicroelectronics |
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STM32MP151AAB3 数据表(HTML) 198 Page - STMicroelectronics |
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198 / 253 page ![]() Electrical characteristics STM32MP151A/D 198/253 DS12500 Rev 3 General PCB design guidelines PCB design guidelines are provided in AN5031 “Getting started with STM32MP1 Series hardware development.” available from the ST website www.st.com. 6.3.23 DAC electrical characteristics Table 78. DAC characteristics(1)(2) Symbol Parameter Conditions Min Typ Max Unit VDDA Analog supply voltage - 1.8 3.3 3.6 V VREF+ Positive reference voltage - 1.80 - VDDA VREF- Negative reference voltage -- VSSA - RL Resistive Load DAC output buffer ON, Not valid in Sample & Hold mode connected to VSSA 5- - kΩ connected to VDDA 25 - - RO Output Impedance DAC output buffer OFF 10.3 13 16 RBON Output impedance sample and hold mode, output buffer ON DAC output buffer ON VDD = 2.7 V - - 1.6 kΩ VDD = 2.0 V - - 2.6 RBOFF Output impedance sample and hold mode, output buffer OFF DAC output buffer OFF VDD = 2.7 V - - 17.8 kΩ VDD = 2.0 V - - 18.7 CL Capacitive Load DAC output buffer OFF - - 50 pF CSH Sample and Hold mode - 0.1 1 µF VDAC_OUT Voltage on DAC_OUT output DAC output buffer ON 0.2 - VDDA - 0.2(3) V DAC output buffer OFF 0 - VREF + tSETTLING Settling time (full scale: for a 12-bit code transition between the lowest and the highest input codes when DAC_OUT reaches the final value of ±1LSB) Normal mode, DAC output buffer ON ±1 LSB - 2 - µs Normal mode, DAC output buffer OFF, +/-1LSB, Cload ≤ 10 pF -- 2 tWAKEUP(4) Wakeup time from off state (setting the Enx bit in the DAC Control register) until the ±1LSB final value Normal mode, DAC output buffer ON -5 7.5 µs Normal mode, DAC output buffer OFF -2 5 PSRR VDDA supply rejection ratio Normal mode DAC output buffer ON --80 -28 dB |
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