STM32MP151AAB3 datasheet(199/253 Pages) STMICROELECTRONICS

199 / 253 page

DS12500 Rev 3

199/253

STM32MP151A/D

Electrical characteristics

232

tSAMP

Sampling time in Sample

and Hold mode

CSH=100nF

(Code transition between

the lowest input code and

the highest input code

when DAC_OUT reaches

final value ± 1LSB)

DACMCR.MODEx[2:0] =

100/101

(BUFFER ON)

-0.7

DACMCR.MODEx[2:0] = 110

(BUFFER OFF)

-11.5-

DACMCR.MODEx[2:0] = 111

(INTERNAL BUFFER OFF)

-0.3

CIint

Internal sample and hold

capacitor

2.2

Voffset

Middle code offset for 1

trim code step

VREF+ = 3.6 V

450

µV

VREF+ = 1.8 V

213

IDDA(DAC)

DAC quiescent

consumption from VDDA

DAC output

buffer ON

No load, middle

code (0x800)

360

µA

No load, worst

code (0xF1C)

490

DAC output

buffer OFF

No load,

middle/worst

code (0x800)

-20-

Sample and Hold mode,

CSH = 100 nF

360×TON/

(TON+TOFF)

(5)

IDDV(DAC)

DAC consumption from

VREF+

DAC output

buffer ON

No load, middle

code (0x800)

170

No load, worst

code (0xF1C)

170

DAC output

buffer OFF

No load,

middle/worst

code (0x800)

160

Sample and Hold mode, Buffer

ON, CSH = 100 nF (worst code)

170×TON/

(TON+TOFF)

(5)

Sample and Hold mode, Buffer

OFF, CSH = 100 nF (worst code)

170×TON/

(TON+TOFF)

(5)

1. Guaranteed by design.

2. Unless otherwise noted, CL ≤ 50 pF with RL ≥ 5 kΩ when DAC output buffer is ON, or CL ≤ 10 pF with no RL when DAC

output buffer is OFF.

3. Since VREF+ must always be ≤ VDDA, maximum VDAC_OUT = minimum value between Max(VREF+) and Max(VDDA-0.2)

4. In buffered mode, the output can overshoot above the final value for low input code (starting from the minimum value).

5. TON is the refresh phase duration, while TOFF is the hold phase duration. Refer to the product reference manual for more

details.

Table 78. DAC characteristics(1)(2) (continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

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