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FXPS7115D4 数据表(PDF) 35 Page - NXP Semiconductors

部件名 FXPS7115D4
功能描述  Digital absolute pressure sensor, 40 kPa to 115 kPa
PDF  72 Pages
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制造商  NXP [NXP Semiconductors]
网页  http://www.nxp.com
标志 NXP - NXP Semiconductors

FXPS7115D4 数据表(HTML) 35 Page - NXP Semiconductors

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NXP Semiconductors
FXPS7115D4
Digital absolute pressure sensor, 40 kPa to 115 kPa
FXPS7115D4
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2019. All rights reserved.
Product data sheet
Rev. 3 — 5 December 2019
35 / 72
Table 41. DEVSTAT3 - device status register (address 04h) bit description
Bit
Symbol
Description
7
MISO_ERR
In SPI mode, the MISO data mismatch flag is set when a MISO Data mismatch fault
occurs. The MISO_ERROR bit is cleared by a read of the DEVSTAT3 register through any
communication interface, or by a status transmission including the error status through the
SPI.
0 — No error detected
1 — MISO data mismatch
6
OSCTRAIN_ERR
The oscillator training error bit is set if an error detected in either the oscillator training
settings, or the master communication timing. Once the error condition is corrected, the
OSCTRAIN_ERR bit is cleared after a read of the OSCTRAIN_ERR bit through any
communication interface, or by a status transmission including the error status through any
communication interface.
0 — No error detected
1 — Oscillator training error
7.7.3 TEMPERATURE - temperature register (address 0Eh)
The temperature register is a read-only register that provides a temperature value for the
IC. The temperature value is specified in the temperature sensor signal chain section of
Table 101.
Note: The device is only guaranteed to operate within the temperature limits specified in
Section 10 "Static characteristics ".
Table 42. TEMPERATURE - temperature register (address 0Eh) bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
TEMP[7:0]
Reset
0
0
0
0
0
0
0
0
Access
R
R
R
R
R
R
R
R
7.7.4 DEVLOCK_WR - lock register writes register (address 10h)
The lock register writes register is a read/write register that contains the ENDINIT bit and
reset control bits.
Table 43. DEVLOCK_WR - lock register writes register (address 10h) bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
ENDINIT
reserved
reserved
reserved
SUP_ERR_DIS
reserved
RESET[1:0]
Factory default
0
0
0
0
0
0
0
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W



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