数据搜索系统，热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

预览 PDF HTML

FXPS7115D4 数据表(PDF) 39 Page - NXP Semiconductors

部件名 FXPS7115D4
功能描述  Digital absolute pressure sensor, 40 kPa to 115 kPa
PDF  72 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  NXP [NXP Semiconductors]
网页  http://www.nxp.com
标志 NXP - NXP Semiconductors

FXPS7115D4 数据表(HTML) 39 Page - NXP Semiconductors

Back Button FXPS7115D4 Datasheet HTML 35Page - NXP Semiconductors FXPS7115D4 Datasheet HTML 36Page - NXP Semiconductors FXPS7115D4 Datasheet HTML 37Page - NXP Semiconductors FXPS7115D4 Datasheet HTML 38Page - NXP Semiconductors FXPS7115D4 Datasheet HTML 39Page - NXP Semiconductors FXPS7115D4 Datasheet HTML 40Page - NXP Semiconductors FXPS7115D4 Datasheet HTML 41Page - NXP Semiconductors FXPS7115D4 Datasheet HTML 42Page - NXP Semiconductors FXPS7115D4 Datasheet HTML 43Page - NXP Semiconductors Next Button
Zoom Inzoom in Zoom Outzoom out
 39 / 72 page
background image
NXP Semiconductors
FXPS7115D4
Digital absolute pressure sensor, 40 kPa to 115 kPa
FXPS7115D4
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2019. All rights reserved.
Product data sheet
Rev. 3 — 5 December 2019
39 / 72
Table 52. SOURCEID_0 - source identification register (address 1Ah) bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
SID0_EN
reserved
reserved
reserved
SOURCEID_0[3:0]
Factory default
0
0
0
0
0
0
0
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 53. SOURCEID_1 - source identification register (address 1Bh) bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
SID1_EN
reserved
reserved
reserved
SOURCEID_1[3:0]
Factory default
0
0
0
0
0
0
0
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7.7.8 TIMING_CFG - communication timing register (address 22h)
The communication timing configuration register is a user programmed read/write
register that contains user-specific configuration information for protocol timing. This
register is included in the read/write array error detection. This register is readable and
writable in SPI mode or I2C mode.
Table 54. TIMING_CFG - communication timing register (address 22h) bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
reserved
OSCTRAIN_
SEL
CK_CAL_
RST
reserved
reserved
CK_CAL_EN
Factory default
0
0
0
0
0
0
0
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7.7.9 SPI Configuration Control Register (SPI_CFG, Address 3Dh)
In SPI mode, the SPI configuration control register is a user programmed read/write
register that contains the SPI protocol configuration information. This register is included
in the read/write array error detection. This register is readable and writable in SPI mode
or I2C mode
Table 55. SPI_CFG Register (address 3Dh) bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
reserved
DATASIZE
SPI_CRC_LEN[1:0]
SPICRCSEED[3:0]
Factory default
0
0
0
0
0
0
0
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7.7.9.1 SPI Data Field Size (DATASIZE)
The SPI data field size bit controls the size of the SPI data field as shown in Table 56.
Table 56. DATASIZE Bit Definition
DATASIZE
SPI Data Field Size
0
12-Bits
1
16-Bits



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com