DP83261AVF datasheet(72/132 Pages) NSC

72 / 132 page

70 Signal Descriptions (Continued)

72 PHY INTERFACE

The PHY Interface signals transfer symbol pairs between the BMAC and PLAYER devices Transfers are synchronous using the

125 MHz Local Byte Clock signal (signal provided by the Clock Distribution Device)

A control bit is used to indicate if a Data symbol pair or Control symbol pair or a mixed ControlData symbol pair are being

transferred

Parity is generated on the PHY

Indicate and MA

Indicate data Parity is checked on the PHY

Request and MA

Request

data

Symbol

Description

PRP

114

PHY Request Parity

Odd parity for PRC and PRD7 – 0

PRC

112

PHY Request Control

0 Indicates PRD7 – 0 contains a Data symbol pair

1 Indicates PRD7 – 0 contains a Control or mixed ControlData symbol pair

PRD7 – 0

110 108

PHY Request Data

Contains a Data or Control symbol pair

105 103

99 97

95 92

PIP

115

PHY Indicate Parity

Odd parity for PIC and PID7 – 0

PIC

113

PHY Indicate Control

0 Indicates PID7 – 0 contains a Data symbol pair

1 Indicates PID7 – 0 contains a Control or mixed ControlData symbol pair

PID7 – 0

111 109

PHY Indicate Data

Contains a Data or a mixed ControlData symbol pair

107 104

102 98

96 93

DP83261AVF 数据表(PDF) 72 Page - National Semiconductor (TI)

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