7

STM32F303 BLOCK DIAGRAM

12-channel DMA

72 MHz

CPU

Nested vector

interrupt

controller (NVIC)

Memory Protection Unit

(MPU)

JTAG/SW debug/ETM

Floating point unit

(FPU)

Flexible Static Memory

Controller (FSMC)

AHB bus matrix

Interconnect matrix

System

RTC/AWU

Power supply

1.8 V regulator

POR/PDR/PVD

Internal RC oscillators

40 kHz + 8 MHz

Clock control

PLL

2x watchdogs

(independent and

window)

Cyclic redundancy

check (CRC)

Xtal oscillators

32 kHz + 4 to 32 MHz

1x SysTick timer

Touch-sensing

controller 24 keys

51/86/115 I/Os

Control

3x 16-bit (144 MHz)

motor control PWM

Synchronized AC timer

1x 32-bit timers

5x 16-bit timers

Up to 16-Kbyte

CCM-SRAM

64 bytes backup register

Up to 512-Kbyte Flash

memory

Up to 64-Kbyte SRAM

Analog

4x 12-bit ADC

40 channels / 5 MSPS

2x 12-bit DAC with

basic timers

Temperature sensor

7x comparators (25 ns)

4x Programmable

Gain Ampliers (PGA)

Connectivity

1x CAN 2.0B

1x USB 2.0 FS

5x USART/UART

LIN, smartcard, IrDA,

modem control

4x SPI,

(with 2x full duplex I²S)

3x I²C

ADVANCED PERIPHERALS

•

Up to seven fast and ultra‑fast

comparators (down to 25 ns)

•

Up to four op amps with

programmable gain (PGA) at 1%

accuracy

•

Up to four ultra‑fast 12‑bit ADCs

with 5 MSPS and 21 ns sampling

time (up to 18 MSPS in Interleaved

mode)

•

Up to three fast 144 MHz motor

control timers (resolution < 7 ns)

•

SRAM with Parity bit and

Polynomial CRC for better

reliability

•

Fast communication peripherals:

9 Mbits/s USART, 18 Mbits/s SPI,

and 1 MHz I²C

•

Full duplex I²S for audio

applications

•

5‑volt tolerant I/Os (FT, Ftf)

The high mathematical computation brought by the Cortex‑M4 core, combined with its rich and advanced analog peripherals set,

make STM32F30x devices ideal for control loops such as in motor control applications.

The routine booster (CCM‑SRAM) accelerates

the execution of critical routines. It consists

of an SRAM plugged on both instruction and

data buses where code is executed without

any wait state, thus providing 43% more

performance compared to Flash execution.

This ‘static cache’ offers 90 DMIPS or

245 CoreMark (equivalent to devices with

CPU frequency > 100 MHz).

Flash memory

Data SRAM

0 Wait state

CCM-SRAM

0 Wait state

63 DMIPS

90 DMIPS

Critical routines

Critical routines

+43%

performance

Cortex-M4 + FPU

Code

Data

CCM-SRAM: THE ROUTINE BOOSTER