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CDP1852CD3 数据表(PDF) 4 Page - Intersil Corporation |
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CDP1852CD3 数据表(HTML) 4 Page - Intersil Corporation |
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4 / 7 page ![]() 4 Static Burn-In Circuit Three-State Output Leakage Low IOZL VDD = 5V, VO = 0V - -1 - -5 µA VDD = 10V, VO = 0V - -1 - -5 µA Three-State Output Leakage High IOZH VDD = 5V, VO = 5V -1 -5 µA VDD = 10V, VO = 10V -1 -5 µA Input Capacitance CIN Note 2 - 10 - 10 pF Output Capacitance COUT Note 2 - 15 - 15 pF NOTES: 1. The CDP1852C/3 meets all 5V static electrical specifications of the CDP1852/3 except +125oC quiescent device current for which the limit is IDD = 300µA. 2. Input and output capacitance are guaranteed but not tested. Static Electrical Specifications VIN = 0 or VDD, Except as Noted (Continued) PARAMETER SYMBOL TEST CONDITIONS LIMITS UNITS -55oC, +25oC+125oC MIN MAX MIN MAX 1 2 3 4 5 6 7 8 9 10 11 12 16 17 18 19 20 21 22 23 24 15 14 13 VDD VDD VSS VSS ALL RESISTORS 47k Ω (±20%) TYPE NO. VDD TEMPERATURE TIME CDP1852/3 11V +125oC 160 Hrs. Min. CDP1852C/3 7V +125oC 160 Hrs. Min. Dynamic Electrical Specifications Mode = 0 Input Port, See Figure 3, Input tr, tf ≤ 15ns; CL = 50pF PARAMETER SYMBOL VDD VOLTS LIMITS (NOTE 1) UNITS -55oC, +25oC +125oC (NOTE 1) MIN MAX (NOTE 1) MIN MAX Select Duration tSW 5 250 - 360 - ns 10 150 - 180 - ns Clock Pulse Width tWW 5 150 - 200 - ns 10 90 - 110 - ns Clear Pulse Width tCLR 5 110 - 160 - ns 10 50 - 80 - ns Data-In to Clock Fall Setup Time tDS 5 -10 - -10 - ns 10 -5 - -5 - ns CDP1852/3, CDP1852C/3 |
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