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CDP1852CD3 数据表(PDF) 6 Page - Intersil Corporation |
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CDP1852CD3 数据表(HTML) 6 Page - Intersil Corporation |
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6 / 7 page ![]() 6 Dynamic Electrical Specification Mode = 1 Output Port, See Figure 4, Input tr, tf ≤ 15ns; C L = 50pF PARAMETER SYMBOL VDD VOLTS LIMITS (NOTE 1) UNITS -55oC, +25oC+125oC (NOTE 1) MIN MAX (NOTE 1) MIN MAX Clock Pulse Width tCLK 5 170 - 260 - ns 10 90 - 130 - ns Write Width Duration tWW 5 200 - 260 - ns 10 110 - 130 - ns Clear Pulse Width tCLR 5 110 - 135 - ns 10 60 - 75 - ns Data-In to Clock Fall Setup Time tDS 5 -10 - -10 - ns 10 -5 - -5 - ns Data Hold from Write Termination tDH 5 130 - 170 - ns 10 70 - 90 - ns Select-After Clock-Fall Hold Time tSH 50 - 0 - ns 10 0 - 0 - ns Propagation Delay Times: Clear to Data tRDO 5 - 215 - 290 ns 10 - 140 - 190 ns Write to Data Out tWDO 5 - 250 - 350 ns 10 - 130 - 190 ns Data In to Data Out tDDO 5 - 150 - 200 ns 10 - 80 - 100 ns Clear to SR tRSR 5 - 175 - 240 ns 10 - 120 - 160 ns Clock to SR tCSR 5 - 170 - 240 ns 10 - 90 - 120 ns Deselect to SR tSSR 5 - 170 - 240 ns 10 - 90 - 120 ns NOTE: 1. Time required by a device to allow for the indicated function. CDP1852/3, CDP1852C/3 |
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