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ADC3541 数据表(PDF) 12 Page - Texas Instruments |
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ADC3541 数据表(HTML) 12 Page - Texas Instruments |
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12 / 68 page  6.8 Timing Requirements Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = – 40°C to TMAX = 105°C, ADC sampling rate = 65 MSPS, 50% clock duty cycle, AVDD, IOVDD = 1.8 V, and –1- dBFS differential input, unless otherwise noted PARAMETER TEST CONDITIONS MIN NOM MAX UNIT ADC Timing Specifications tAD Aperture delay TBD ns tAD Aperure delay variation TBD ns tA Aperture jitter square wave clock with fast edges 180 fs tACQ Signal acquisition period, referenced to sampling clock falling edge FS = 10 Msps -TS/2 Sampling Clock Period FS = 25 Msps -TS/2 FS = 65 Msps -TS/4 tCONV Signal conversion period, referenced to sampling clock falling edge FS = 10 Msps +TS × 1/5 Sampling Clock Period FS = 25 Msps +TS × 3/8 FS = 65 Msps +TS × 5/8 Wake up time Time to valid data after coming out of power down. Internal reference. Bandgap reference enabled, single ended clock TBD us Bandgap reference enabled, differential clock TBD Bandgap reference disabled, single ended clock TBD ms Bandgap reference disabled, differential clock TBD Time to valid data after coming out of power down. External 1.6V reference. Bandgap reference enabled, single ended clock 9.5 us Bandgap reference enabled, differential clock 14 Bandgap reference disabled, single ended clock TBD ms Bandgap reference disabled, differential clock TBD tS,SYNC Setup time for SYNC input signal Referenced to sampling clock rising edge 500 ps tH,SYNC Hold time for SYNC input signal 600 ADC Latency Signal input to data output SDR CMOS 1 Clock cycles DDR CMOS 1 Serialized CMOS: 2-wire 2 Serialized CMOS: 1-wire 1 Add. Latency Real decimation by 2 21 Output clock cycles Complex decimation by 2 22 Real or complex decimation by 4, 8, 16, 32 23 Scrambling 3 ADC3541 SBAS840 – JULY 2020 www.ti.com 12 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADC3541 |
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