USB7002 datasheet(33/56 Pages) MICROCHIP

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DS00002670D-page 33

USB7002

7.4.2

RECEIVE OPERATION

Data is sampled into the RX Shift Register using the Receive clock, divided by 16. The Receive clock is provided by the

Baud Rate Generator. A filter is used to remove spurious inputs that last for less than two periods of the Receive clock.

When the complete word has been clocked into the receiver, the data bits are transferred to the RX Buffer Register or

to the RX FIFO (if enabled) to be read by the CPU. (The first bit of the data to be received is placed in bit 0 of this reg-

ister.) The receiver also checks that the parity bit and stop bits are as specified by the Line Control Register.

If enabled, an RX Data Received interrupt will be generated when the data has been transferred to the RX Buffer Reg-

ister or, if FIFOs are enabled, when the RX Trigger Level has been reached. Interrupts can also be generated to signal

RX FIFO Character Timeout, incorrect parity, a missing stop bit (frame error) or other Line Status errors.

When FIFOs are enabled (i.e. bit 0 of the FIFO Control Register is set), the UART can store up to 16 bytes of received

data at a time. Depending on the selected RX Trigger Level, interrupt will go active to indicate that data is available when

the RX FIFO contains 1, 4, 8 or 14 bytes of data.

USB7002 数据表(PDF) 33 Page - Microchip Technology