USB7002 datasheet(15/56 Pages) MICROCHIP

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 2018-2019 Microchip Technology Inc.

DS00002670C-page 15

USB7002

Note 3-1

Configuration strap values are latched on Power-On Reset (POR) and the rising edge of RESET_N

(external chip reset). Configuration straps are identified by an underlined symbol name. Signals that

function as configuration straps must be augmented with an external resistor when connected to a

load. For additional information, refer to Section 3.3, Configuration Straps and Programmable

Functions.

Configuration Straps

Port 4-1 D+

Disable

Configuration

Strap

PRT_DIS_P[4:1]

Port 4-1 D+ Disable Configuration Strap.

These configuration straps are used in conjunction with

the corresponding PRT_DIS_M[4:1] straps to disable

the related port (4-1). See Note 3-1.

Both USB data pins for the corresponding port must be

tied to 3.3V to disable the associated downstream port.

Port 4-1 D-

Disable

Configuration

Strap

PRT_DIS_M[4:1]

Port 4-1 D- Disable Configuration Strap.

These configuration straps are used in conjunction with

the corresponding PRT_DIS_P[4:1] straps to disable the

related port (4-1). See Note 3-1.

Both USB data pins for the corresponding port must be

tied to 3.3V to disable the associated downstream port.

Non-Removable

Ports

Configuration

Strap

CFG_NON_REM

Non-Removable Ports Configuration Strap.

This configuration strap controls the number of reported

non-removable ports. See Note 3-1.

Battery Charging

Configuration

Strap

CFG_BC_EN

I/O12

Battery Charging Configuration Strap.

This configuration strap controls the number of BC 1.2

enabled downstream ports. See Note 3-1.

Device Mode

Configuration

Straps 3-1

CFG_STRAP[3:1]

Device Mode Configuration Straps 3-1.

These configuration straps are used to select the

device’s mode of operation. See Note 3-1.

Power/Ground

+3.3V I/O Power

Supply Input

VDD33

+3.3 V power and internal regulator input.

+1.2V Core

Power Supply

Input

VDD12

+1.2 V digital core power supply input.

Ground

VSS

Common ground.

This exposed pad must be connected to the ground

plane with a via array.

TABLE 3-1:

PIN DESCRIPTIONS (CONTINUED)

Name

Symbol

Buffer

Type

Description

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